Multiple duty cycle tap points for a precise and programmable duty cycle generator

• US 6,577,202 B1
• Filed: 12/14/2001
• Issued: 06/10/2003
• Est. Priority Date: 12/14/2001
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Correale, Anthony Jr., Atallah, Francois I.
• Primary Examiner(s): Mis, David C.
• Application Number:
  US10/020,533
• Publication Number:
  US 20030112083A1
• Time in Patent Office: 543 Days
• Field of Search: 331/57, 327/155, 327/159, 327/172, 327/175, 327/176, 327/261, 327/263, 327/264, 327/269-277, 327/285
• US Class Current: 331/57
• CPC Class Codes: H03B 28/00 Generation of oscillations by methods not covered by groups H03B5/00 - H03B27/00, including modification of the waveform to produce sinusoidal oscillations analogue function generators for performing computing operations G06G7/26; use of transformers for conversion of waveform in ac-ac converters H02M5/18

Abstract

A precise programmable duty cycle generator employs multiple duty cycle generators connected in series to provide multiple duty cycle tap point outputs, each with a known and precise value of a duty cycle from a source input signal having any duty cycle. The present invention transforms an incoming signal'"'"'s duty cycle to a known value by a first programmable duty cycle generator, and then applies the output of the first programmable duty cycle generator to a second programmable duty cycle generator which provides multiple duty cycle tap point outputs, each having a different known value of a precise duty cycle.

Claims

1. A programmable circuit for generating a plurality of output clock signals, each having a different desired duty cycle, comprising:

a first duty cycle generator for converting an input clock signal of unknown duty cycle to a known and programmable duty cycle;

a second programmable duty cycle generator connected in series with the output of the first duty cycle generator, and providing multiple tap point output signals, each with a known and precise duty cycle value.

2. The circuit of claim 1, wherein the second duty cycle generator comprises:

an operational amplifier for comparing an analog voltage representing the desired duty cycle with an analog feedback voltage, and generating an output control signal in response thereto;

a voltage controlled duty cycle generator, responsive to the output control signal of the operational amplifier and having an input clock signal, for generating an output clock signal having the desired duty cycle, wherein the voltage controlled duty cycle generator comprises a plurality of stages; and

a low pass filter, responsive to the output clock signal, for measuring the duty cycle of the output clock signal and for generating the analog feedback voltage for the operational amplifier, thereby providing a closed feedback loop operation.

3. The circuit of claim 2, wherein the second duty cycle generator comprises:

an n-bit digital to analog converter for converting a digitally encoded desired duty cycle into the analog voltage.

4. The circuit of claim 2, wherein the first duty cycle generator comprises:

an operational amplifier for comparing an analog voltage representing the desired duty cycle with an analog feedback voltage, and generating an output control signal in response thereto;

a voltage controlled duty cycle generator, responsive to the output control signal of the operational amplifier and having an input clock signal, for generating an output clock signal having the desired duty cycle, wherein the voltage controlled duty cycle generator comprises a plurality of stages; and

a low pass filter, responsive to the output clock signal, for measuring the duty cycle of the output clock signal and for generating the analog feedback voltage for the operational amplifier, thereby providing a closed feedback loop operation.

5. The circuit of claim 4, wherein the first duty cycle generator comprises:

an n-bit digital to analog converter for converting a digitally encoded desired duty cycle into an analog voltage.

6. The circuit of claim 1, including a buffer at each tap point output to isolate the output load from the internal circuit of the second duty cycle generator.

7. The circuit of claim 6, wherein the duty cycle offset due to each buffer is compensated for by the insertion of a like buffer in the feedback loop.

8. The circuit of claim 3, wherein the second duty cycle generator includes a register for storing a set of register bits representative of the digitally encoded desired duty cycle which provides an input to the digital to analog converter.

9. The circuit of claim 5, wherein the first duty cycle generator includes a register for storing a set of register bits representative of the digitally encoded desired duty cycle and providing an input to the digital to analog converter.

10. The circuit of claim 4, wherein each operational amplifier comprises an operational transconductance amplifier for generating an output current proportional to a difference of its input voltages;

and

a capacitor for receiving the generated output current and for charging or discharging the capacitor to produce a voltage across the capacitor which controls the voltage controlled duty cycle generator.

11. The circuit of claim 4, wherein the output of each digital to analog converter is applied to a noninverting input of the operational amplifier, and the output of the low pass filter is applied to an inverting input of the operational amplifier, such that the voltage controlled duty cycle generator inverts the clock signal to produce the output clock signal.

12. The circuit of claim 4, wherein each voltage controlled duty cycle generator comprises a plurality of stages, each of which comprises a current starved inverter, comprised of PFET current sources and NFET current sources followed by a series inverter which presents a capacitive load to the current sources, to provide either additive or subtractive duty cycle corrections, the plurality of current starved inverters being controlled by the output control signal voltage of the operational amplifier which is connected to both the PFET current sources and the NFET current sources, and as the output control voltage increases, the PFET current sources provide a smaller current to charge the capacitive load, and the NFET current sources provide a larger current to discharge the capacitive load, such that the output waveform has a slow rising edge and a fast falling edge, and the difference in edge rates causes the output of the inverter to have a longer falling delay than a rising delay to produce a duty cycle that is controlled by the output control signal voltage of the operational amplifier.

13. The circuit of claim 12, wherein each plurality of stages is followed by an inverter.

14. The circuit of claim 4, wherein each low pass filter comprises an RC low pass filter.