Electro-optical device substrate, electro-optical device and electronic device having dummy layers, and projection display device incorporating the same

• US 6,577,371 B2
• Filed: 02/08/2002
• Issued: 06/10/2003
• Est. Priority Date: 06/17/1997
• Status: Expired due to Term

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Hirabayashi, Yukiya
• Primary Examiner(s): CHOWDHURY, TARIFUR RASHID
• Application Number:
  US10/067,915
• Publication Number:
  US 20020097367A1
• Time in Patent Office: 487 Days
• Field of Search: 349/149, 349/153, 349/155, 349/138, 349/139, 257/59, 257/72
• US Class Current: 349/149
• CPC Class Codes: G02F 1/133357 Planarisation layers
• CPC Class Codes: G02F 1/136209 Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• CPC Class Codes: G02F 1/136277 formed on a semiconductor substrate, e.g. of silicon
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

In a liquid crystal panel substrate having a layered film structure of interlayer insulation films and metal layers alternately formed on a semiconductor substrate provided with a transistor region for pixel selection thereon, to provide a configuration for achieving a uniform polishing rate without thickening of the interlayer insulation film to be polished. A liquid crystal panel substrate is provided with a shading film 12 composed of a second metal layer in a pixel region, a second interlayer insulation film 11 under the shading film, a wiring film 10 composed of a first metal layer under the second interlayer insulation film, a pixel electrode composed of a third metal layer on a third interlayer insulation film 13 on the shading film, and a connecting plug 15 connecting the wiring film 10 and the pixel electrode through an opening provided in the shading film 12. A lower dummy pattern A composed of the first metal layer and an upper dummy pattern B composed of the second metal layer are formed on the periphery of input terminal pads 26 in the non-pixel region. Since the surface level of the third interlayer insulation film 13 formed on the dummy patterns A and B is raised, excessive polishing is prevented at the position. As a result, a uniform polishing rate is achieved in CMP treatment.

Claims

1. An electro-optical device substrate having a non-pixel region and a pixel region, said substrate comprising:

a layered film structure including a plurality of interlayer insulation films and a plurality of conductive layers alternately formed in said pixel region of said substrate, said plurality of conductive layers including a top conductive layer, at least one of said plurality of interlayer insulation films below said top conductive layer being polished;

a plurality of switching elements formed in said pixel region; and

a driver circuit arranged on a periphery of said pixel region and supplying signals to said plurality of switching elements, at least one of said plurality of conductive layers forming a plurality of dummy patterns below said polished interlayer insulation film and positioned in a periphery of said driver circuit.

2. An electro-optical device comprising:

the electro-optical device substrate of claim 1;

a transparent substrate spaced from said electro-optical device substrate; and

an electro-optical material positioned between said electro-optical device substrate and said transparent substrate.

3. An electronic display device comprising the electro-optical device of claim 2.

4. A projection display device comprising a light valve using the electro-optical device of claim 2.