Pulse with modulation control circuit for a high frequency series resonant AC/DC converter

• US 6,577,517 B2
• Filed: 07/30/2001
• Issued: 06/10/2003
• Est. Priority Date: 07/31/2000
• Status: Expired due to Term

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: Chippower.Com, Inc.
• Inventors: Zhang, Haibo, Jain, Praveen Kumar
• Primary Examiner(s): Riley, Shawn
• Application Number:
  US09/916,583
• Publication Number:
  US 20020012260A1
• Time in Patent Office: 680 Days
• Field of Search: 363/89, 363/21.06, 363/21.14, 363/53, 363/127
• US Class Current: 363/89
• CPC Class Codes: H02M 1/38 Means for preventing simultaneous conduction of switches
• CPC Class Codes: H02M 7/217 using semiconductor devices only
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A pulse width modulation control circuit for a high frequency series resonant AC/DC converter suitable for use in computing and network equipment such as personal computers, servers and high-speed routers includes an auxiliary transformer, a zero crossing detector, a delay circuit, a synchronization circuit and an output circuit.

Claims

1. A control circuit for an alternating current (AC) to direct current (DC) converter, comprising a delay circuit for introducing a delay in the generation of gating signals for controlled switches of the converter so that zero crossing detection is pre-processed and compensation for inherent delays in circuits used to generate the gating signals is introduced, the delay circuit causing a leading edge of the gating signals to be in phase and synchronized with zero crossings of the AC input voltage to a terminal of the rectifier switches.

3. A control circuit as claimed in claim 1, wherein the control circuit further comprises:

an auxiliary transformer for receiving AC input voltage and outputting a first plurality of signals;

zero-crossing detector for receiving and modifying the first plurality of signals and outputting a second plurality of signals;

the delay circuit for delaying the second plurality of signals for a predetermined time and outputting a third plurality of signals;

a synchronization circuit for receiving and modifying the third plurality of signals and outputting a fourth plurality of signals; and

an output circuit for receiving the fourth plurality of signals and outputting a plurality of signals for driving a plurality of switches of a synchronous rectifier.

4. The control circuit as claimed in claim 3 wherein the plurality of switches are field effect transistors.

5. The control circuit as claimed in claim 1 wherein the delay circuit comprises:

a first diode having a cathode connected to a first input node and an anode connected to a first output node;

a first resistor having a first terminal connected to the input node and a second terminal connected to the first output node;

a first capacitor having a first terminal connected to the first output node and a second terminal connected to a reference node;

second diode having a cathode connected to a second input node and an anode connected to a second output node;

a second resistor having a first terminal connected to the input node and a second terminal connected to the second output node; and

a second capacitor having a first terminal connected to the second output node and a second terminal connected to the reference node,

whereby a first of the second plurality of signals is received by the first input node;

a second of the second plurality of signals is received by the second input node;

a first of the third plurality of signals is output on the first output node; and

, a second of the third plurality of signals is output on the second output node.

6. The control circuit as claimed in claim 3 wherein the zero-crossing detector comprises:

a first resistor having a first terminal connected to a first input node and a second terminal connected to a first node;

a first diode having a cathode connected to the first node and an anode connected to a reference node;

a second resistor having a first terminal connected to the first node and a second terminal connected to the reference node;

first logic gate having an input connected to the first node and an output connected to a first output node;

a third resistor having a first terminal connected to a second input node and a second terminal connected to a second node;

a second diode having a cathode connected to the second node and an anode connected to the reference node;

a fourth resistor having a first terminal connected to the second node and a second terminal connected to the reference node;

a second logic gate having an input connected to the second node and an output connected to a second output node;

whereby a first of the first plurality of signals is received by the first input node;

a second of the first plurality of signals is received by the second input node;

a first of the third plurality of signals is output on the first output node; and

, a second of the third plurality of signals is output on the second output node.

7. The control circuit as claimed in claim 6 wherein the first and second diodes are zener diodes.

8. The control circuit as claimed in claim 6 wherein the first and second logic gates are AND gates.

9. The control circuit as claimed in claim 3 wherein the synchronization circuit comprises:

a first NOR gate having a first input connected to a first input node, a second input connected to a second output node and an output connected to a first output node;

a second NOR gate having a first input connected to the first output node, a second input connected to a second input node and an output connected to the second output node;

a logic gate having a first input connected to the first input node, a second input connected to the second input node and an output connected to a first node;

a third NOR gate having a first input connected to the first node, a second input connected to a third node and an output connected a third output node;

an inverter having an input connected to the first node and an output connected to a second node;

a diode having a cathode connected to the second node and an anode connected to the third node;

a resistor having a first terminal connected to the second node and a second terminal connected to the third node; and

a capacitor having a first terminal connected to the third node and a second terminal connected to a reference node,

whereby a first of the third plurality of signals is received by the first input node;

a second of the third plurality of signals is received by the second input node;

a first of the fourth plurality of signals is output on the first output node; and

, a second of the fourth plurality of signals is output on the second output node; and

a clock signal is output on the third output node.

10. The control circuit as claimed in claim 9 wherein the Eli logic gate is a NOR gate.

11. The control circuit as claimed in claim 9 wherein the logic gate is a NAND gate.

12. The control circuit as claimed in claim 3 wherein the zero-crossing detector comprises:

a first resistor having a first terminal connected to a first input node and a second terminal connected to a first node;

a second resistor having a first terminal connected to a first reference node and a second terminal connected to a second node;

a third resistor having a first terminal connected to the second node and a second terminal connected to a second reference node;

a first comparator having a positive input connected to the first node, a negative input connected to the second node and an output connected to a first output node;

a fourth resistor having a first terminal connected a second input node and a second terminal connected to a third node;

a fifth resistor having a first terminal connected to the first reference node and a second terminal connected to a fourth node;

a sixth resistor having a first terminal connected to the fourth node and a second terminal connected to the second reference node;

a second comparator having a positive input connected to the third node, a negative input connected to the fourth node and an output connected to a second output node;

whereby a first of the first plurality of signals is received by the first input node;

a second of the first plurality of signals is received by the second input node;

a first of the second plurality of signals is output on the first output node; and

, a second of the second plurality of signals is output on the second output node.

13. The control circuit as claimed in claim 12 wherein the first reference node has a potential of about 5 volts with respect to the second reference node.

14. The control circuit as claimed in claim 3 wherein the zero-crossing detector comprises:

first resistor having a first terminal connected to a first input node and a second terminal connected to a first node;

a second resistor having a first terminal connected to a first reference node and a second terminal connected to a second node;

a third resistor having a first terminal connected to the second node and a second terminal connected to a second reference node;

a first comparator having a negative input connected to the first node, a positive input connected to the second node and an output connected to a first output node;

a fourth resistor having a first terminal connected a second input node and a second terminal connected to a third node;

a fifth resistor having a first terminal connected to the first reference node and a second terminal connected to a fourth node;

a sixth resistor having a first terminal connected to the fourth node and a second terminal connected to the second reference node;

a second comparator having a negative input connected to the third node, a positive input connected to the fourth node and an output connected to a second output node;

whereby a first of the first plurality of signals is received by the first input node;

a second of the first plurality of signals is received by the second input node;

a first of the second plurality of signals is output on the first output node; and

, a second of the second plurality of signals is output on the second output node.

15. The control circuit as claimed in claim 14 wherein the first reference node has a potential of about 5 volts with respect to the second reference node.

16. The control circuit as claimed in claim 1 wherein the control circuit comprises discrete electrical components.

17. The control circuit as claimed in claim 1 wherein the control circuit comprises one of an application specific integrated circuit (ASIC) and an integrated circuit (IC).

2. A control circuit for an alternating current (AC) to direct current (DC) converter, comprising a delay circuit for delaying first and second converter switch gating signals generated by a zero-voltage crossing detector by a time period:

18. A control circuit for an alternating current (AL) to direct current (DC) converter, comprising:

a zero-voltage detector circuit for detecting zero crossings of an AC input voltage to the converter; and

a delay circuit for delaying a gating signal for a first switch of the converter during a positive cycle of the AC input voltage to the converter, and for delaying a gating signal for a second switch of the converter during a negative cycle of the AC input voltage, so that zero voltage crossing detection is pre-processed and compensation for converter switching circuit delays is introduced during generation of the respective gating signals, to ensure that the first and second switches are switched at zero crossings of the AC input voltage and cross-conduction between the first and second switches is avoided.

19. A method of controlling switches in a converter for converting an AC (alternating current) to a DC (direct current) comprising steps of:

a) detecting zero-crossings of an AC input voltage to the converter; and

b) after detecting a zero-crossing of the input AC voltage, generating a gating signal for a first switch of the converter during a positive half-cycle of the input voltage to the converter, and generating a gating signal for a second switch of the converter during a negative half-cycle of the input voltage, so that zero voltage crossing detection is pre-processed and compensation for converter switching circuit delays is introduced during generation of the respective gating signals to ensure that the first and second switches are switched at zero crossings of the AC input voltage and cross-conduction between the first and second switches is avoided.