Non-volatile semiconductor memory device with programming voltage generating system and data programming method

• US 6,577,539 B2
• Filed: 10/11/2001
• Issued: 06/10/2003
• Est. Priority Date: 08/27/1993
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Iwahashi, Hiroshi
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US09/975,631
• Publication Number:
  US 20020041518A1
• Time in Patent Office: 607 Days
• Field of Search: 365/185.28, 365/185.24, 365/185.3, 365/189.09
• US Class Current: 365/185.28
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

On a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of “0” or “1” of the binary data are stored much in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the data latch circuits can be formed at any positions remote from the memory cell array.

Claims

1. A non-volatile semiconductor memory device comprising:

a memory cell array including memory cells arranged in matrix form having row lines and column lines, each of the memory cells including a cell transistor having a floating gate and a control gate, and storing data in accordance with a storage state of charges of the floating gate, the memory cells in the same row being commonly connected to one of the row lines, the memory cells in the same column being commonly connected to one of the column lines;

row selection means, connected to the row lines, for selecting one of the row lines;

programming means for programming a memory cell, the programming means injecting electrons to a floating gate to program desired data to the memory cell; and

programming voltage generating means, connected to the row selection means, for generating a programming voltage for injecting electrons to the floating gate, the programming voltage being generated at a first node, the programming voltage generating means including a transistor and voltage control transistors, the transistor having a drain, a source and a gate, the transistor being connected between the first node and a power supply node,

wherein the programming voltage has a plurality of voltage levels, the voltage levels of the programming voltage are generated by selectively turning on the voltage control transistors and changing a gate voltage of the transistor, the programming voltage is applied to the row selection means, and the programming voltage having one of the voltage levels is applied to the selected row line by the row selection means to inject electrons to the floating gate.

2. The non-volatile semiconductor memory device according to claim 1, further comprising at least a first resistance means and a second resistance means the first resistance means and the second resistance means each having a plurality of resistances the first resistance means being connected to the second resistance means, the connecting point of the first resistance means and the second resistance means being connected to the gate of the transistor, wherein in order to change the gate voltage of the transistor, a resistance value of the first resistance means or the second resistance means is changed by substantially changing the number of the resistances of the first resistance means or the second resistance means.

3. A non-volatile semiconductor memory device comprising:

a memory cell array including memory cells arranged in matrix form having row lines and column lines, each of the memory cells including a cell transistor having a floating gate and a control gate, and storing data in accordance with a storage state of charges of the floating gate, the memory cells in the same row being commonly connected to one of the row lines, the memory cells in the same column being commonly connected to one of the column lines;

row selection means, connected to the row lines, for selecting one of the row lines;

programming means for programming a memory cell, the programming means injecting electrons to a floating gate to program desired data to the memory cell; and

programming voltage generating means, connected to the row selection means, for generating a programming voltage and for injecting electron to the floating gate, the programming voltage generating means including voltage control transistors and at least a first resistance means and a second resistance means, the first resistance means being connected to the second resistance means the first resistance means and the second resistance means each having a plurality of resistances,

wherein the programming voltage has a plurality of voltage levels, the voltage levels of the programming voltage are generated by selectively turning on the voltage control transistors and changing a resistance value of the first resistance means or the second resistance means, the programming voltage is applied to the row selection means, and the programming voltage having one of the voltage levels is applied to the selected row line by the row selection means to inject electrons to the floating gate, wherein the number of the resistances of the first resistance means or the second resistance means is substantially changed in order to change the resistance value of the first resistance means or the second resistance means.

4. A non-volatile semiconductor memory device comprising:

a memory cell array including memory cells arranged in matrix form having row lines and column lines, each of the memory cells including a cell transistor having a floating gate and a control gate, and storing data in accordance with a storage state of charges of the floating gate, the memory cells in the same row being commonly connected to one of the row lines, the memory cells in the same column being commonly connected to one of the column lines;

row selection means, connected to the row lines, for selecting one of the row lines;

programming means for programming the memory cell, the programming means injecting electrons to a floating gate to program desired data to the memory cell; and

programming voltage generating means connected to the row selection means, for generating a programming voltage for injecting electrons to the floating gate, the programming voltage generating means including a plurality of resistance means having a total resistance value,

wherein the programming voltage has a plurality of voltage levels, the voltage levels of the programming voltage are generated by changing the total resistance value of the plurality of resistance means, the programming voltage is applied to the row selection means, and the programming voltage having one of the voltage levels is applied to the selected row line by the row selection means to inject electrons to the floating gate.

5. A non-volatile semiconductor memory device comprising:

a memory cell array including memory cells arranged in matrix form having row lines and column lines, each of the memory cells including a cell transistor having a floating gate and a control gate, and storing data in accordance with a storage state of charges of the floating gate, the memory cells in the same row being commonly connected to one of the row lines, the memory cells in the same column being commonly connected to one of the column lines;

a row selection transistor, connected to the row lines, for selecting one of the row lines;

a programming circuit for programming a memory cell, the programming circuit injecting electrons to a floating gate to program desired data to the memory cell; and

a programming voltage generating circuit, connected to the row selection transistor, for generating a programming voltage for injecting electrons to the floating gate, the programming voltage being generated at a first node, the programming voltage generating circuit including a programming voltage generating circuit transistor and voltage control transistors, the programming voltage generating circuit transistor having a drain, a source and a gate, the programming voltage generating circuit transistor being connected between the first node and a power supply node,

wherein the programming voltage has a plurality of voltage levels, the voltage levels of the programming voltage are generated by selectively turning on the voltage control transistors and changing a gate voltage of the programming voltage generating circuit transistor, the programming voltage is applied to the row selection transistor, and the programming voltage having one of the voltage levels is applied to the selected row line by the row selection transistor to inject electrons to the floating gate.

6. The non-volatile semiconductor memory device according to claim 5, further comprising at least a first resistor and a second resistor, the first resistor and the second resistor each including a plurality of resistors the first resistor being connected to the second resistor, the connecting point of the first resistor and the second resistor being connected to the gate of the programming voltage generating circuit transistor, wherein the resistance value of the first resistor or the second resistor is variable for changing the gate voltage of the programming voltage generating circuit transistor, wherein the number of the resistors of the first resistor or the second resistor is substantially changed in order to change the resistance value of the first resistor or the second resistor.

7. A non-volatile semiconductor memory device comprising:

a memory cell array including memory cells arranged in matrix form having row lines and column lines, each of the memory cells including a cell transistor having a floating gate and control gate, and storing data in accordance with a storage state of charges of the floating gate, the memory cells in the same row being commonly connected to one of the row lines, the memory cells in the same column being commonly connected to one of the column lines;

a row selection transistor, connected to the row lines, for selecting one of the row lines;

a programming circuit for programming a memory cell, the programming circuit injecting electrons to a floating gate to program desired data to the memory cell; and

a programming voltage generating circuit, connected to the row selection transistor, for generating a programming voltage and for injecting electrons to the floating gate, the programming voltage generating circuit including voltage control transistors and at least a first resistor and a second resistor, the first resistor being connected to the second resistor, the first resistor and second resistor each having a plurality of resistances,

wherein the programming voltage has a plurality of voltage levels, the voltage levels of the programming voltage are generated by changing a resistance value of the first resistor or the second resistor, the programming voltage is applied to the row selection transistor, and the programming voltage having one of the voltage levels is applied to the selected row line by the row selection transistor to inject electrons to the floating gate, wherein the number of the resistances of the first resistors or the second resistor is substantially changed in order to change the resistance value of the first resistor or the second resistor.

8. A non-volatile semiconductor memory device comprising:

a memory cell array including memory cells arranged in matrix form having row lines and column lines, each of the memory cells including a cell transistor having a floating gate and a control gate, and storing data in accordance with a storage sate of charges of the floating gate, the memory cells in the same row being commonly connected to one of the row lines, the memory cells in the same column being commonly connected to one of the column lines;

a row selection transistor, connected to the row lines, for selecting one of the row lines;

a programming circuit for programming a memory cell, the programming circuit injecting electrons to a floating gate to program desired data to the memory cell; and

a programming voltage generating circuit, connected to the row selection transistor, for generating a programming voltage and for injecting electrons to the floating gate, the programming voltage generating circuit including a plurality of resistors having a total resistance value,

wherein the programming voltage has a plurality of voltage levels, the voltage levels of the programming voltage are generated by changing the total resistance value of the plurality of resistors, the programming voltage is applied to the row selection transistor, and the programming voltage having one of the voltage levels is applied to the selected row line by the row selection transistor to inject electrons to the floating gate.

9. A non-volatile semiconductor memory device comprising:

a memory cell array including memory cells arranged in matrix form having row lines and column lines, each of the memory cells including a cell transistor having a floating gate and a control gate, and storing data in accordance with a storage state of charges of the floating gate, the memory cells in the same row being commonly connected to one of the row lines, the memory cells in the same column being commonly connected to one of the column lines;

a row selection transistor, connected to the row lines, for selecting one of the row lines;

a programming circuit for programming a memory cell, the programming circuit injecting electrons to a floating gate to program desired data to the memory cell; and

a programming voltage generating circuit including a control signal generating circuit and a variable programming voltage generating circuit, said control signal generating circuit outputting a plurality of control signals each having a different voltage level, said variable programming voltage generating circuit outputting a programming voltage corresponding to the voltage level of a control signal supplied from said control signal generating circuit to an output terminal, and said programming voltage being applied to said row selection transistor for injecting electrons to the floating gate.

10. The non-volatile semiconductor memory device according to claim 9, wherein said variable programming voltage generating circuit includes a transistor to a gate of which the control signal is applied, one end of which is connected to a power source, the other end of which is connected to the output terminal, and which outputs the programming voltage corresponding to the voltage level of the control signal applied to the gate of the transistor to the output terminal.

11. The non-volatile semiconductor memory device according to claim 9, said variable programming voltage generating circuit includes a plurality of transistors and a plurality of switches, the control signals each having a different voltage level being applied to gates of the corresponding transistors, one end of each transistor being connected to a power supply, the other end of each transistor being connected to a corresponding one of the switches, each of the transistors outputting a programming voltage, a value of which corresponds to the voltage level of the control signal applied, the other ends of the switches begin commonly connected to the output terminal, and one of the switches being selectively turned on to output the programming voltage from one of the transistors to the output terminal.

12. The non-volatile semiconductor memory device according to claim 11, wherein said control signal generating circuit includes a plurality of series-connected voltage-dividing resistors positioned between a high voltage power supply and a low voltage power supply, junction points between two adjacent voltage-dividing resistors being control signal outputting terminals connected to the gates of the transistors, the control signal outputting terminals outputting divided voltages as the control signals.

13. The non-volatile semiconductor memory device according to claim 12, wherein the first switch is connected in series with said voltage-dividing resistors.

14. The non-volatile semiconductor memory device according to claim 13, wherein:

a second switch is provided between the output terminal and another high voltage power supply;

the first switch and the second switch are alternately turned on and off; and

a voltage for read-out is supplied via the second switch.

15. A non-volatile semiconductor memory device comprising:

a memory cell array including memory cells arranged in matrix form having row lines and column lines, each of the memory cells including a cell transistor having a floating gate and a control gate, and storing data in accordance with a storage state of charges of the floating gate, the memory cells in the same row being commonly connected to one of the row lines, the memory cells in the same column being commonly connected to one of the column lines;

a row selection transistor, connected to the row lines, for selecting one of the row lines;

a programming circuit for programming a memory cell, the programming circuit injecting electrons to a floating gate to program desired data to the memory cell; and

a programming voltage generating circuit including a plurality of resistor devices with switches, one end commonly connected to a first power supply, the other end commonly connected to one end of a resistor element, the other end of the resistor element serving as a programming voltage outputting terminal and being connected to a second power supply, a predetermined number of said resistor devices with switches being turned on, a voltage division being carried out by one or more turned-on resistor devices with switches and said resistor element, and a voltage produced at the programming voltage outputting terminal due to the voltage division being applied to said row selection transistor as a programming voltage.

16. The non-volatile semiconductor memory device according to claim 15, wherein said resistor devices with switches are transistors.

17. The non-volatile semiconductor memory device according to claim 15, wherein:

another voltage power supply is connected to the programming voltage outputting terminal via a read-out switch so as to supply a voltage for read-out; and

the switches of the resistor devices and the read-out switch are alternately turned on and off.