Method and system for reconfigurable channel coding

• US 6,577,678 B2
• Filed: 05/08/2001
• Issued: 06/10/2003
• Est. Priority Date: 05/08/2001
• Status: Expired due to Term

• Current Assignee: Cornami, Inc.
• Original Assignee: QuickSilver Technology
• Inventors: Scheuermann, W. James
• Primary Examiner(s): VO, DON NGUYEN
• Application Number:
  US09/851,543
• Publication Number:
  US 20020168018A1
• Time in Patent Office: 763 Days
• Field of Search: 375/219, 375/259, 375/285, 375/295, 375/222, 375/316, 455/418, 714/795
• US Class Current: 375/222
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0059 Convolutional codes
• CPC Class Codes: H04L 65/75 Media network packet handling
• CPC Class Codes: H04L 65/756 adapting media to device capabilities

Abstract

Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder element.

Claims

1. A reconfigurable system for providing channel coding in a wireless communication device comprising:

a plurality of computation elements for performing channel coding operations;

memory for storing programs to control each of the plurality of computation elements; and

a controller for controlling the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communications standards, wherein the plurality of computational elements further comprises a data reordering element, wherein the plurality of computation elements further comprises a linear feedback shift register (LFSR) element, wherein the plurality of computation elements further comprises a convolutional encoder element, wherein the convolutional encoder further comprises an input shift register, a delay register, a plurality of polynomial generators, a rate selector means, a multiplexer, and an output shift register.

2. The reconfigurable system of claim 1 further comprising a host controller for reconfiguring the channel coding by providing programs that update the stored programs to accommodate a change in the wireless standard.

3. The reconfigurable system of claim 1 wherein each of the plurality of computation elements further comprises a finite state machine.

4. The reconfigurable system of claim 1 wherein the data reordering element further comprises a counter, a look-up table, a data input source, a multiplexer, a stager, and a data output source.

5. The reconfigurable system of claim 1 wherein the LFSR element further comprises a register, a shifter, a multiplexer, an exclusive-OR logic means, and an accumulator.

6. The reconfigurable system of claim 5 wherein the LFSR element operates in a byte-oriented manner.

7. The reconfigurable system of claim 1 wherein each of the plurality of polynomial generators further comprises a configuration register, an AND logic means, and an exclusive-OR logic means.

8. The reconfigurable system of claim 7 wherein the convolutional encoder operates in a byte-oriented manner.

9. The reconfigurable system of claim 1 wherein the plurality of computation elements further comprises a Viterbi decoder element.

10. The reconfigurable system of claim 9 wherein the Viterbi decoder element further comprises a coupled configuration of a counter, a codeword and punctures look-up table, a register, recode logic, an address generator, path metrics memory, state registers, plus/minus adjusters, adders, a selector, and a comparator.