Clock recovery in multi-carrier transmission systems

• US 6,577,690 B1
• Filed: 06/15/1999
• Issued: 06/10/2003
• Est. Priority Date: 06/25/1998
• Status: Expired due to Term

• Current Assignee: Silicon Automation Systems Limited
• Original Assignee: Silicon Automation Systems Limited
• Inventors: Barman, Kaushik, Arvind, Mandayam T.
• Primary Examiner(s): BAYARD, EMMANUEL
• Application Number:
  US09/333,801
• Time in Patent Office: 1,456 Days
• Field of Search: 375/219, 375/222, 375/221, 375/220, 375/240.28, 375/254, 375/285, 375/346, 375/356, 375/358, 375/381, 375/316, 370/210, 370/278, 370/281, 370/282, 370/286, 370/289, 370/295
• US Class Current: 375/354
• CPC Class Codes: H04L 27/261 Details of reference signals
• CPC Class Codes: H04L 27/2659 Coarse or integer frequency offset determination and synchronisation
• CPC Class Codes: H04L 27/266 Fine or fractional frequency offset determination and synchronisation
• CPC Class Codes: H04L 27/2675 Pilot or known symbols
• CPC Class Codes: H04L 27/2679 Decision-aided

Abstract

A method and apparatus is provided that computes an optimal estimate of known clock frequency error between the transmitter and receiver using a known pilot signal and the statistics of the noise process. The estimate is computed such that the residual clock error is below the least count (the smallest frequency correction that can be imparted) of the VCXO that controls the receiver sample clock. A tracking technique based on a measure of drift in taps of frequency domain equalizers of different sub-carriers is disclosed. This tracking ensures that the residual mean square error is within a predefined bound. Finally, the least count effects in digitally controlled oscillators (DAC controlled VCXOs and Numerically Controlled Oscillators (NCXO)) are addressed by a dithering mechanism. The dithering mechanism involves imparting positive and negative clock corrections for different lengths of time in such a manner that the residual clock error becomes zero mean. In data mode, a tracking scheme makes uses of variations in frequency domain equalizer taps for determination of clock error estimates, computes a residual clock error estimate different from the clock error estimate generated from pilot channel using training mode scheme, and SNR based combination of errors is computed to obtain clock correction, and a dithering mechanism computes the actual correction to be given to the VCXO such that the residual phase error is maintained at an acceptably low value.

Claims

1. A method for generating a clock error estimate in order to synchronize a receiver clock with a transmission clock in a multi-carrier transmission system in which possibly colored noise is introduced during the transmission of a data signal, comprising:

receiving a pilot signal in a predetermined sub-carrier frequency;

determining the signal-to-noise ratio of the pilot signal;

determining noise characteristics of the pilot signal; and

filtering the pilot signal to generate a clock error estimate responsive to the signal-to-noise ratio, the noise characteristics and a predefined estimation error.

2. The method of claim 1 wherein computing the signal-to-noise ratio comprises:

determining discrete Fourier transform coefficients of the pilot signal.

3. The method of claim 1 wherein determining noise characteristics further comprises:

determining discrete Fourier transform coefficients of the pilot signal; and

determining autocorrelation statistics of the noise responsive to the determined discrete Fourier transform coefficients.

4. The method of claim 1 in which the receiver clock is generated by a control system further comprising:

generating a predefined estimation error responsive to a least count of the receiver clock control system.

5. The method of claim 1 in which a received pilot test signal further comprising:

sampling the received pilot signal and accompanying noise;

receiving a test signal having signal characteristics of the predetermined pilot signal prior to transmission of the predetermined pilot signal to the receiving system, wherein said test signal is generated locally to the receiving system;

determining a phase rotation of the received pilot signal responsive to comparing a phase of the received pilot signal with a phase of the test signal; and

wherein determining a signal-to-noise ratio of the pilot signal further comprises determining the signal-to-noise ratio of the received pilot signal responsive to the phase rotation of the received pilot signal.

6. The method of claim 5 wherein determining noise characteristics of the pilot signal further comprises determining the noise characteristics of the pilot signal responsive to the phase rotation of the received pilot signal.

7. The method of claim 1 further comprising:

sampling the pilot signal;

determining a least count value for the receiving clock system; and

wherein filtering the pilot signal to generate a clock error estimate responsive to the signal-to-noise ratio, the noise characteristics and a predefined estimation error further comprises;

computing a number of taps and weights of the taps for a linear estimate filter responsive to the least count value, the signal-to-noise ratio, the noise characteristics, and samples of the pilot signal.

8. The method of claim 7 wherein the samples are delayed prior to computing the taps and weights of the filter.

9. A method of correcting residual clock error in a multi-carrier transmission system in which data signals are transmitted to a receiving system and are sampled in accordance with an output of a receiving clock system, comprising:

generating an initial clock error estimate;

adjusting the output of the receiving clock system responsive to the generated initial clock error estimate;

receiving data signals from the transmission system;

measuring drift in frequency domain taps of the receiving system to obtain an estimate of the residual clock error;

adjusting the receiving clock system output responsive to the estimated residual clock error; and

sampling the data signals in accordance with the adjusted receiving clock system output.

10. The method of claim 9 further comprising:

dithering the estimate of the residual clock error to minimize phase error build-up;

and adjusting further comprises;

adjusting the receiving clock system output responsive to the dithered residual clock error estimate.

11. The method of claim 10 wherein dithering the estimate of the residual clock error further comprises:

determining a least count of the receiving clock system;

dithering the estimate of the residual clock error responsive to the residual clock error estimate being below the least count.

12. The method of claim 11 wherein dithering comprises:

receiving estimated clock correction values;

storing the estimated clock correction values;

storing the estimated clock correction values to be transmitted to the receiving clock system;

resetting a counter responsive to a clock correction value to be transmitted being non-zero;

incrementing the counter responsive to a clock correction value to be transmitted being equal to zero;

transmitting a non-zero clock correction to the receiving clock system responsive to a value of the counter exceeding a predetermined threshold.

13. The method of claim 12 wherein the non-zero clock correction transmitted to the receiving clock system has a magnitude equal to the least count value of the receiving clock system and a sign equal to a most recent estimated clock correction transmitted to the receiving clock system.

14. The method of claim 9 further comprising:

receiving a pilot signal;

computing a clock error estimate responsive to the pilot signal;

combining the clock error estimate computed from the pilot signal with the estimated residual clock error; and

wherein adjusting further comprises;

adjusting the receiving clock system output responsive to the combined clock error estimate and the residual clock error estimate.

15. An apparatus for generating a clock error estimate in order to synchronize a receiver clock with a transmission clock in a multi-carrier transmission system in which possibly colored noise is introduced during the transmission of a data signal, comprising:

a data sampler, for sampling an input pilot signal of a predetermined carrier frequency in accordance with a clock signal received from a receiver clock system;

a phase rotation analyzer, coupled to the data sampler and a test pilot signal input for comparing a phase of the input pilot signal to a phase of the test pilot signal to determine a phase rotation of the input pilot signal, wherein the test pilot signal has substantially the same phase as the input pilot signal prior to transmission of the input pilot signal;

a signal-to-noise ratio estimator, coupled to the phase rotation analyzer, for computing a signal-to-noise ratio for the input pilot signal responsive to the phase rotation of the input pilot signal;

a noise characteristic estimator, coupled to the phase rotation analyzer, for computing noise characteristics of the input pilot signal responsive to the phase rotation of the input pilot signal;

a linear filter, coupled to the noise characteristic estimator, the signal-to-noise ratio estimator, the phase rotation an analyzer, and to which a least count value of the receiver clock system is input, for computing a number of taps and weights of the taps responsive to the signal-to-noise ratio estimate, the noise characteristic estimate, the least count value, and the samples received from the phase rotation analyzer to generate a linear estimate of the clock error;

the receiver clock system, having a clock control input coupled to the output of the linear filter, for adjusting an output clock signal responsive to the clock error estimate generated by the linear filter.

16. The apparatus of claim 15 wherein the phase rotation analyzer further comprises:

a discrete fourier transform module, coupled to the output of the data sampler, for determining discrete fourier transform coefficients for the input pilot signal;

a rotation comparator, coupled to the discrete fourier transform module and a test pilot signal, for computing a difference in phase between the test pilot signal and the input pilot signal;

a modified phase rotation estimator, coupled to the rotation comparator, for multiplying the difference in phase between the test pilot signal and the input pilot signal with a complex conjugate of a previous sample of the test pilot signal to generate a modified phase rotation value; and

an arctan computation block, coupled to the modified phase rotation estimator, for computing a difference between consecutive phase values of the input signal responsive to modified phase rotation value.

17. The apparatus of claim 15 further comprising:

a ditherer, coupled to the linear filter, for receiving the clock error estimate, and generating a dithered clock estimate output responsive to a value of the clock error estimate.

18. The apparatus of claim 17 wherein the ditherer receives a least count value from the receiving clock system, and the ditherer further comprises:

an input cyclic buffer, for receiving and storing the value of the clock error estimate;

an actual correction buffer, coupled to the input cyclic buffer, for receiving the value of the clock error estimate, transmitting a dithered clock correction value to the receiving clock system responsive to receiving a dithered clock correction value from a dither analyzer, transmitting the value of the clock error estimate otherwise, and storing the transmitted clock correction value;

the dither analyzer, coupled to the input cyclic buffer and a counter, for resetting a counter responsive to the value of the clock error estimate being non-zero, incrementing the counter responsive to the value of the clock error estimate being zero, comparing the counter value to a predetermined threshold value, and transmitting a dithered clock correction value to the actual correction buffer responsive the value of the counter exceeding the threshold.

19. The apparatus of claim 18 wherein the dithered clock correction value is a non-zero value.