Binary self-correcting phase detector for clock and data recovery

• US 6,577,694 B1
• Filed: 11/08/1999
• Issued: 06/10/2003
• Est. Priority Date: 11/08/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Meghelli, Mounir
• Primary Examiner(s): Pham, Chi
• Assistant Examiner(s): TRAN, KHANH C
• Application Number:
  US09/435,838
• Time in Patent Office: 1,310 Days
• Field of Search: 375/359, 375/355, 375/360, 375/362, 375/371, 375/373, 375/375, 327/9, 327/12, 327/10, 327/42, 327/43, 327/93, 327/141, 327/142, 327/147, 327/156, 327/162, 327/159
• US Class Current: 375/373
• CPC Class Codes: H03D 13/003 in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means

Abstract

A phase detector for a clock and data recovery circuit from random non-return-to zero (NRZ) data signal includes a plurality (e.g., preferably three) edge-triggered flip-flops. The incoming NRZ data are sampled by a pair of edge-triggered flip-flops using the transition of the clock generated by the clock recovery circuit. A third edge-triggered flip-flop processes the outputs from the edge-triggered flip-flop pair to indicate whether the generated clock leads or lags the received data.

Claims

1. A phase detector, comprising:

a first flip-flop for sampling an incoming data signal in accordance with a local clock signal to produce a first sampled data signal;

a second flip-flop for sampling said incoming data signal in accordance with said local clock signal to produce a second sampled data signal;

a third flip-flop for sampling said second sampled data signal with said first sampled data signal to produce a binary control signal; and

an inverter which is provided to receive an output from the first flip-flop and to provide an input to the third flip-flop.

2. The phase detector according to claim 1, wherein said binary control signal comprises an early-late control signal representing whether rising edges of the local clock signal are early or late with respect to transitions of the incoming data signal sampled.

3. The phase detector according to claim 1, wherein said incoming data signal comprises a Non-Return-to-Zero data stream.

9. The phase detector according to claim 1, wherein an output of said first flip-flop and an output of said second flip-flop are identical to one another and shifted by a predetermined period of said local clock signal.

10. The phase detector according to claim 9, wherein said predetermined period is one-half period of said local clock signal.

4. A phase detector circuit used in a clock and data recovery system for synchronizing a received non-return-to-zero (NRZ) data signal with a clock signal generated by a clock source, said clock signal having a period equal to the unit bit interval of said received NRZ data signal, said phase detector for regenerating said received NRZ data signal using said clock signal, said phase detector comprising:

a first flip-flop, including data and clock input terminals for respectively receiving a. data input and a clock input, and an output terminal for providing an output;

a second flip-flop, including data and clock input terminals for respectively receiving said data input and an inverted clock input, and an output terminal for providing an output;

a third flip-flop, including data and clock input terminals for respectively receiving an output from said second flip-flop and an inverted output from said first flip-flop, and an output terminal for providing an output.

5. The phase detector according to claim 4, further comprising:

a data signal input device for supplying said data input; and

a clock signal input for supplying said clock input.

6. The phase detector according to claim 4, further comprising:

a first inverter including an input terminal for receiving said clock input and for providing said inverted clock input to said second flip-flop.

7. The phase detector according to claim 6, further comprising:

a second inverter including an input terminal for receiving said output from said first flip-flop and for providing said inverted output to said clock terminal of said third flip-flop.

8. The phase detector according to claim 4, wherein said data input terminal of said third flip-flop receives said output of said second flip-flop.

11. A phase detector, comprising:

a data signal input for supplying input data and opposite phase input data of said input data;

a clock signal input for supplying an input clock and an opposite phase input clock of said input clock;

a first flip-flop, including differential data D and DB input terminals, differential clock C and CB input terminals and differential Q and QB output terminals, said first flip-flop receiving input data at said differential data input terminals and said input clock at said differential clock input terminals;

a second flip-flop, including differential data D and DB input terminals, differential clock C and CB input terminals and differential Q and QB output terminals, said second flip-flop receiving input data at said differential data input terminals and said input clock at said differential clock input terminals; and

a third flip-flop, including differential data D and DB input terminals, differential clock C and CB input terminals and differential Q and QB output terminals, said third flip-flop receiving a differential output from said second flip-flop at said differential data input terminals of said third flip-flop and receiving a differential output from said first flip flop at differential clock input terminals of said third flip-flop.

12. The phase detector according to claim 11, further comprising:

means for connecting said input data to said D input terminal of said first flip-flop; and

means for connecting said opposite phase input data to said DB input terminal of said first flip-flop.

13. The phase detector according to claim 11, further comprising:

means for connecting said input data to said D input terminal of said second flip-flop; and

means for connecting said opposite phase input data to said DB input terminal of said second flip-flop.

14. The phase detector according to claim 11, further comprising:

means for connecting said input clock to said C input terminal of said first flip-flop; and

means for connecting said opposite phase input clock to said CB input terminal of said first flip-flop.

15. The phase detector according to claim 11, further comprising:

means for connecting said input clock to said CB input terminal of said second flip-flop; and

means for connecting said opposite phase input clock to said C input terminal of said second flip-flop.

16. The phase detector according to claim 11, further comprising:

means for connecting said Q output terminal of said first flip-flop to said CB input terminal of said third flip-flop; and

means for connecting said QB output terminal of said first flip-flop to said C input terminal of said third flip-flop.

17. The phase detector according to claim 11, further comprising:

means for connecting said Q output terminal of said second flip-flop to said D input terminal of said third flip-flop; and

means for connecting said QB output terminal of said second flip-flop to said DB input terminal of said third flip-flop.

18. A phase detector, comprising:

means for sampling an incoming data signal in accordance with a local clock signal to produce a first sampled data signal;

means for sampling said incoming data signal in accordance with said local clock signal to produce a second sampled data signal;

means for sampling said second sampled data signal with said first sampled data signal to produce an early-late control signal; and

an inverter which is provided to receive an output from said means for sampling said incoming data signal, and to provide an input to said means for sampling said second sampled data signal.

19. A system for recovering a clock signal from transmitted data, comprising:

a phase detector circuit including a plurality of edge-triggered flip-flops,

wherein incoming data are sampled by first and second flip-flops of said plurality of flip-flops by using a transition of a clock generated by the system, and

wherein a third edge-triggered flip-flop of said plurality of flip-flops processes outputs from said first and second flip-flops to indicate whether the generated clock leads or lags the incoming data received,

said system further comprising an inverter which is provided to receive an output from said first flip-flop, and to provide an input to the third edge-triggered flip flop.

20. The system according to claim 19, wherein said transmitted data comprises Non-Return-to-Zero (NRZ) data.

21. A method of data and/or clock recovery, comprising:

sampling an incoming data signal in accordance with a local clock signal to produce a first sampled data signal;

sampling said incoming data signal in accordance with said local clock signal to produce a second sampled data signal; and

sampling said second sampled data signal with said first sampled data signal to produce a binary control signal,

wherein said first sampled data signal is inverted to clock said sampling of said second sampled data signal.

22. A method for regenerating a data signal and/or recovering a clock signal, said method comprising:

passing the data signal through a parallel connection of first and second D-type flip-flops each including data input, clock input and output terminals;

using the signals appearing at the output terminal of the first D-type flip-flop to sample the signals appearing at the output terminal of the second D type flip-flop through a third D-type flip-flop including data input, clock input, and output terminals;

integrating the signals appearing at the output terminal of the third D-type flip-flop to provide a control voltage;

generating a variable frequency output signal in response to the value of said control voltage; and

clocking the clock input terminals of said first and second D-type flip-flops as a function of said variable frequency output signal.