Emulating narrow band phase-locked loop behavior on a wide band phase-locked loop

• US 6,577,695 B1
• Filed: 03/04/1997
• Issued: 06/10/2003
• Est. Priority Date: 03/04/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Level One Communications, Inc. (Intel Corporation)
• Inventors: Parker, James, Everitt, James
• Primary Examiner(s): Le, Amanda T.
• Application Number:
  US09/526,794
• Time in Patent Office: 2,289 Days
• Field of Search: 375/375, 375/376, 331/11, 331/16, 331/17, 331/25, 331/163, 327/150, 327/151, 327/156, 327/159, 327/145, 327/147
• US Class Current: 375/375
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H03L 7/14 for assuring constant frequency when supply or correction voltages fail or are interrupted
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A phase-locked loop circuit for providing a tightly controlled capture range for locking an output signal to a data signal, while also providing a wide frequency capture range for initially pulling the output signal within this narrow, predetermined frequency range. The apparatus detects a frequency difference between at least one reference signal and an output signal, and generates a frequency error signal in response to the frequency difference. A phase difference is detected between a received input signal and the output signal, and a phase error signal is generated in response to the phase difference. The frequency error signal and the phase error signal are combined to control the frequency of the output signal by controlling an input-controlled oscillator.

Claims

1. A phase-locked loop (PLL), comprising:

frequency compare means for detecting a frequency difference between a PLL output signal and a combination of a first and a second reference signal, and for generating a frequency error signal in response thereto;

phase error detection means for detecting a phase difference between a received input signal and the PLL output signal, and for generating a phase error signal in response thereto;

signal summing means, coupled to the phase error detection means and the frequency compare means, for combining the phase error signal and the frequency error signal to form a combined error signal, wherein the frequency compare means increases the amplitude of the frequency error signal to create a frequency error signal that overdrives the phase error signal when the frequency difference is outside of a predetermined frequency range; and

a input-controlled oscillator having an input terminal coupled to receive the combined error signal and an output terminal to output the PLL in response thereto.

2. The phase-locked loop as in claim 1, wherein the amplitude of the frequency error signal is increased so that it overdrives the phase error signal.

3. The phase-locked loop as in claim 1, wherein the frequency compare means comprises an up/down counter for detecting when the variable PLL output signal is outside a predetermined frequency range.

4. The phase-locked loop as in claim 1, wherein the frequency compare means comprises means for detecting the frequency difference in a first frequency range, and wherein the phase error detection means comprises means for detecting the phase difference when the frequency difference is within the first frequency range.

5. The phase-locked loop as in claim 1, wherein:

a frequency variance between the combination of the two reference signals and the PLL output signal defines a frequency variance range; and

the frequency error signal is recognized by the signal summing means when the frequency variance is beyond the frequency variance range, and the phase error signal is recognized by the signal summing means when the frequency variance is within the frequency variance range.

6. The phase-locked loop as in claim 1, further comprising an integrator coupled between the signal summing means and the input-controlled oscillator to provide a second-order PLL.

7. The phase-locked loop as in claim 1, wherein the frequency compare means, the phase error detection means, the signal summing means, and the input-controlled oscillator are applied to any order PLL.

8. The phase-locked loop as in claim 1, wherein the magnitude of the frequency error signal is proportional to the magnitude of the frequency difference between the at least one reference signal and the PLL output signal.

9. The phase-locked loop as in claim 1, wherein:

the frequency compare means comprises an n-bit counter having the at least one reference signal and the PLL output signal as inputs; and

the value of the frequency error signal is dependent on the counter value.

10. A multiple-stage phase-locked loop (PLL) having an inherently wide actual signal capture range and a narrow effective signal capture range, the phase-locked loop comprising:

first detection means for detecting frequency differences between an output signal and a combination of a first and a second reference signal, and for generating a frequency error signal when the frequency differences fall outside of a predetermined frequency range;

second detection means for detecting second phase differences between a received input signal and the output signal, and for generating a phase error signal in response thereto;

signal summing means, coupled to the first detection means and the second detection means, for combining the frequency error signal and the phase error signal, wherein the phase error signal is overdriven with the frequency error signal when both the frequency error signal and the phase error signal are active; and

input-controlled oscillation means, coupled to the signal summing means, for controlling the frequency of the output signal in response to the frequency and phase error signals.

11. The multiple-stage phase-locked loop as in claim 10, wherein the first and second detection means detect the frequency and phase differences concurrently.

12. The multiple-stage phase-locked loop as in claim 10, wherein the first detection means comprises means for generating a dominating error signal by changing an amplitude of the frequency error signal.

13. The multiple-stage phase-locked loop as in claim 12, wherein the signal summing means comprises means for combining the dominating error signal and the phase error signal, and for overdriving the phase error signal with the dominating error signal.

14. The multiple-stage phase-locked loop as in claim 10, wherein the input-controlled oscillation means comprises means for first controlling the frequency of the output signal in response to the frequency error signal, and for subsequently controlling the frequency of the output signal in response to the phase error signal.

15. The multiple-stage phase-locked loop as in claim 10, wherein the first detection means, the second detection means, the signal summing means, and the input-controlled oscillation means are used in conjunction with any order PLL.

16. The multiple-stage phase-locked loop as in claim 10, wherein the magnitude of the frequency error signal is proportional to the magnitude of the frequency difference.

17. The multiple-stage phase-locked loop as in claim 10, wherein the first detection means comprises counting means for varying an up/down count based upon the frequency differences between the at least one reference signal and the output signal, and for generating the frequency error signal when the up/down count is outside of a predetermined count range which corresponds to the predetermined frequency range.

18. The multiple-stage phase-locked loop as in claim 17, wherein the counting means generates a positive first phase error signal when the up/down count is above an upper count of the predetermined count range.

19. The multiple-stage phase-locked loop as in claim 18, wherein the positive frequency error signal causes the frequency of the output signal to increase.

20. The multiple-stage phase-locked loop as in claim 17, wherein the counting means generates a negative first phase error signal when the up/down count is below a lower count of the predetermined count range.

21. The multiple-stage phase-locked loop as in claim 20, wherein the negative frequency error signal causes the frequency of the output signal to decrease.

22. A method for phase-locking an output signal to a data signal, comprising the steps of:

generating a frequency error signal where a frequency difference, measured by the frequency difference between the output signal and a plurality of frequency-regulated reference signals, is outside of a predetermined frequency range;

generating a phase error signal for a phase difference, measured by the phase difference between the data signal and the output signal;

overdriving the phase error signal with the frequency error signal when the frequency difference is outside of the predetermined frequency range; and

controlling the frequency of the output signal with the phase error signal and the frequency error signal.

23. The method of claim 22, wherein the overdriving step comprises the step of increasing the amplitude of the frequency error signal to overdrive the phase error signal.

24. The method of claim 22, wherein the step of generating a frequency error signal comprises the steps of varying an up/down count based upon the frequency differences between the reference signal and the output signal, and for generating the frequency error signal when the up/down count is outside of a predetermined count range corresponding to the predetermined frequency range.