×

Emulating narrow band phase-locked loop behavior on a wide band phase-locked loop

  • US 6,577,695 B1
  • Filed: 03/04/1997
  • Issued: 06/10/2003
  • Est. Priority Date: 03/04/1997
  • Status: Expired due to Term
First Claim
Patent Images

1. A phase-locked loop (PLL), comprising:

  • frequency compare means for detecting a frequency difference between a PLL output signal and a combination of a first and a second reference signal, and for generating a frequency error signal in response thereto;

    phase error detection means for detecting a phase difference between a received input signal and the PLL output signal, and for generating a phase error signal in response thereto;

    signal summing means, coupled to the phase error detection means and the frequency compare means, for combining the phase error signal and the frequency error signal to form a combined error signal, wherein the frequency compare means increases the amplitude of the frequency error signal to create a frequency error signal that overdrives the phase error signal when the frequency difference is outside of a predetermined frequency range; and

    a input-controlled oscillator having an input terminal coupled to receive the combined error signal and an output terminal to output the PLL in response thereto.

View all claims
  • 7 Assignments
Timeline View
Assignment View
    ×
    ×