Pipelined discrete cosine transform apparatus

• US 6,577,772 B1
• Filed: 12/31/1998
• Issued: 06/10/2003
• Est. Priority Date: 12/23/1998
• Status: Expired due to Fees

• Current Assignee: LG Electronics, Inc. (LG Corporation)
• Original Assignee: LG Electronics, Inc. (LG Corporation)
• Inventors: Lee, Joo Heung
• Primary Examiner(s): Johnson, Timothy M.
• Assistant Examiner(s): Bayat, Ali
• Application Number:
  US09/224,743
• Time in Patent Office: 1,622 Days
• Field of Search: 382/250, 382/251, 382/253, 382/232, 375/240.04, 348/403.1, 708/402, 708/403, 708/404, 708/405, 708/406, 708/400
• US Class Current: 382/250
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: H04N 19/122 Selection of transform size, e.g. 8x8 or 2x4x8 DCT; Selection of sub-band transforms of varying structure or type
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

The present invention relates to a DCT operator for compressing image data through dividing the image data into various frequency components by using a spatial correlation on a screen, particularly to be fit with a low-power required mobile video terminal.

Therefore, the present invention provides a DCT operator, in which a range of DCT coefficients for a calculation is controllable among an entire DCT region, and also provides, in another embodiment, a 2D DCT device including a first 1D DCT operator for executing a 1D DCT operation in rows about input image data; a transposition memory for temporarily storing a result of the 1D DCT operator; a second 1D DCT operator for executing a 1D DCT operation in columns about the resultant data processed by the 1D DCT operation in rows and stored in the transposition memory; and a timing control logic unit for controlling operation of the first and second 1D DCT operators and the transposition memory according to a DCT block size control signal given from outside.

Claims

1. A two-dimensional (2D) discrete cosine transform (DCT) device comprising:

a first one-dimensional (1D) operator for executing a 1D DCT operation in rows for input image data;

a transposition memory for temporarily storing resultant data of the first 1D DCT operator;

a second 1D DCT operator for executing a 1D DCT operation in columns for the resultant data of the first 1D DCT operator and stored in the transposition memory;

a control logic unit for controlling operation of the first and second 1D DCT operators and the transposition memory according to an external DCT block control signal; and

a coding controller for controlling the external DCT block control signal according to information of quantized DCT coefficients.

2. A 2D DCT device according to claim 1, wherein the first 1D DCT operator comprises:

a DCT kernel bank controller for controlling an operating range of DCT coefficients according to a control signal from the control logic unit; and

a DCT kernel bank for storing DCT kernel values,

wherein the DCT kernel bank controller designates a desired DCT kernel value in the DCT kernel bank, and

wherein the DCT kernel bank outputs the DCT kernel value designated by the DCT kernel bank controller.

3. A 2D DCT device according to claim 2, wherein the first 1D DCT operator further comprises:

an adding/subtracting unit having a plurality of adders and subtractors therein for respectively adding/subtracting components of the input image data symmetrically with a cosine function to produce added and subtracted data; and

a multiplexing unit having a plurality of multiplexers therein for selecting one of the added and subtracted data according to a select signal from the DCT kernel bank controller; and

a multiplying unit having a plurality of multipliers therein for multiplying the selected one of the added and subtracted data by the DCT kernel value output from the DCT kernel bank.

4. A 2D DCT device according to claim 2, wherein the second 1D DCT operator comprises:

a DCT kernel bank controller for controlling an operating range of DCT coefficients according to a control signal from the control logic unit; and

a DCT kernel bank for storing DCT kernel values,

wherein the DCT kernel bank controller designates a desired DCT kernel value in the DCT kernel bank, and

wherein the DCT kernel bank outputs the DCT kernel value designated by the DCT kernel bank controller.

5. A 2D DCT device according to claim 1, wherein the control logic unit comprises:

a write address generating unit for providing write control signals to the transposition memory;

a read address generating unit for providing write control signals to the transposition memory; and

a timing signal generating unit for providing timing signals to control the first and second 1D DCT operators.

6. A DCT calculator including the 2D DCT device of claim 1, and further comprising:

a counter for counting non-zero quantized DCT coefficients; and

a coding controller for generating the DCT block control signal.

7. A DCT calculator, comprising:

input means for receiving input data;

a DCT operator for performing a DCT calculation on the received input data; and

a controller for controlling a range of DCT coefficients employed in the DCT calculation, wherein the controller outputs to the DCT operator a number of DCT coefficients which are desired for the DCT calculation and wherein an upper limit of the number of DCT coefficients is set by an external control signal.

8. The DCT calculator of claim 7, wherein the controller controls the range of DCT coefficients in response to an external control signal.

9. The DCT calculator of claim 8, wherein the range of DCT coefficients is determined by characteristics of the input data.

10. The DCT calculator of claim 8, wherein the characteristics of the input data are estimated from a statistical property of previously calculated DCT coefficients.

11. The DCT calculator of claim 10, wherein the statistical property of the previously calculated DCT coefficients is a number of non-zero quantized DCT coefficients in a previous data block.

12. The DCT calculator of claim 10, wherein the statistical property of the previously calculated DCT coefficients is a number of non-zero quantized DCT coefficients in a previous data frame.

13. The DCT calculator of claim 8, wherein the characteristics of the input data is a coding mode for a corresponding macro block of data.

14. The DCT calculator of claim 7, further comprising a DCT kernel bank for storing DCT kernels, wherein the controller provides a control signal to the DCT kernel bank and the DCT kernel bank outputs corresponding DCT kernels according to the control signal.

15. The DCT calculator of claim 14, wherein the DCT kernel bank includes multiplexers for outputting the corresponding DCT kernels according to the control signal from the controller.

16. The DCT calculator of claim 14, wherein when the input data includes N data values input at a same time, then N/2 elements of the DCT kernel are selected at the same time.

17. The DCT calculator of claim 14, further comprising:

an adder/subtractor having for adding/subtracting values of the input data in pairs; and

a multiplying unit for multiplying output values of the adder/subtractor by the DCT kernels output from the DCT kernel bank.

18. The DCT calculator of claim 14, wherein when the input data includes N data values input at a same time, then a number of multiplying operations for obtaining one of the DCT coefficients is reduced to N/2 multiplications by adding/subtracting input data in pairs.

19. A discrete cosine transform (DCT) calculator comprising:

input means for receiving input image data;

a two dimensional (2D) DCT device, coupled to the input means, for performing a DCT calculation with respect to the input image data in response to a DCT block control signal;

a quantizer, coupled to the 2D DCT device, for generating DCT coefficients by quantizing resultant data of the DCT calculation in response to a quantizer block control signal;

a counter, coupled to the quantizer, for generating a count signal by counting non-zero DCT coefficients from the DCT coefficients; and

a coding controller, coupled between the 2D DCT device and the counter, for generating the DCT block control signal and the quantizer block control signal in response to the count signal.

20. A DCT calculator according to claim 19, wherein the coding controller further generates the DCT block control signal and the quantizer block control signal in response to the input image data.

21. A DCT calculator according to claim 19, wherein the 2D DCT device comprises:

a first one-dimensional (1D) operator for executing a 1D DCT operation in rows for the input image data;

a transportation memory for temporarily storing resultant data of the first 1D DCT operator;

a second 1D DCT operator for executing a 1D DCT operation in columns for the resultant data of the first 1D DCT operator stored in the transportation memory to generate the resultant data of the DCT calculation; and

a control logic unit for controlling operation of the first and second 1D DCT operators and the transposition memory in response to the DCT block control signal.

22. A DCT calculator according to claim 21, wherein the first 1D DCT operator further comprises:

a DCT kernel bank controller for controlling an operating range of DCT coefficients according to a control signal from the control logic unit; and

a DCT kernel bank for storing DCT kernel values, wherein the DCT kernel bank controller designates a desired DCT kernel value in the DCT kernel bank; and

wherein the DCT kernel outputs the DCT kernel value designated by the DCT kernel bank controller.

23. A DCT calculator according to claim 22, wherein the first 1D DCT operator further comprises:

an adding/subtracting unit having a plurality of adders and subtractors therein for respectively adding/subtracting components of the input image symmetrically with a cosine function to produce added and subtracted data;

a multiplexing unit having a plurality of multiplexers therein for selecting one of the added and subtracted data according to a select signal from the DCT kernel bank controller; and

a multiplying unit having a plurality of multipliers therein for multiplying the selected one of the added and subtracted data by the DCT kernel value output from the DCT kernel bank.

24. A DCT calculator according to claim 21, wherein the second 1D DCT operator comprises:

a DCT kernel bank controller for controlling an operating range of DCT coefficients according to a control signal from the control logic unit; and

a DCT kernel bank for storing DCT kernel values, wherein the DCT kernel bank controller designates a desired DCT kernel value in the DCT kernel bank; and

wherein the DCT kernel bank outputs the DCT kernel value designated by the DCT kernel bank controller.

25. A DCT calculator according to claim 21, wherein the control logic unit comprises:

a write address generating unit providing write control signals to the transposition memory;

a read address generating unit for providing read control signals to the transposition memory; and

a timing signal generating unit for providing timing signals to control the first and second 1D DCT operators.

26. A two-dimensional (2D) discrete cosine transform (DCT) device comprising:

a coding controller for controlling a block size of a DCT operating unit and sending a DCT block size control signal;

a first one-dimensional (1D) operator for executing a 1D DCT operation in rows for input image data;

a transposition memory for temporarily storing resultant data of the first 1D DCT operator;

a second 1D DCT operator for executing a 1D DCT operation in columns for the resultant data of the first 1D DCT operator and stored in the transposition memory; and

a control logic unit for controlling operation of the first and second 1D DCT operators and the transposition memory according to the DCT block control signal;

wherein the coding controller controls the DCT block size control signal according to information of the quantized DCT coefficients.

27. The two-dimensional (2D) discrete cosine transform (DCT) device according to claim 26, wherein the first 1D DCT operator comprises:

a DCT kernel bank controller for controlling an operating range of DCT coefficients according to the DCT block control signal from the control logic unit; and

a DCT kernel bank for storing DCT kernel values;

wherein the DCT kernel bank controller designates a desired DCT kernel value in the DCT kernel bank; and

wherein the DCT kernel bank outputs the DCT kernel value designated by the DCT kernel bank controller.