Digital audio signal processors

• US 6,577,910 B1
• Filed: 10/23/1998
• Issued: 06/10/2003
• Est. Priority Date: 10/24/1997
• Status: Expired due to Term

• Current Assignee: Sony United Kingdom Limited (Sony Group Corp.)
• Original Assignee: Sony United Kingdom Limited (Sony Group Corp.)
• Inventors: Eastty, Peter Charles, Thorpe, Peter Damien, Sleight, Christopher
• Primary Examiner(s): Harvey, Minsun Oh
• Application Number:
  US09/178,341
• Time in Patent Office: 1,691 Days
• Field of Search: 700/94, 341/61, 341/143, 341/144, 341/155, 341/126
• US Class Current: 700/94
• CPC Class Codes: H04H 60/04 Studio equipment; Interconnection of studios

Abstract

A digital audio signal processor processes digital audio signals having a first sampling rate S1. The processor has a multiplicity of manually adjustable controls (403) for setting desired parameters of signals to be processed. Sampling means (404) sample each control (403) setting at a second sampling rate S2 less than the first rate S1 to determine the settings thereof. Applying means (401) responsive to the sampling means apply the sampled settings to the signals. For each control the applying means determines the difference of successive samples of setting and applies to the signal, subject to control by that control, increments of setting each increment being a predetermined fraction 1/n of the said difference at a rate nS2 which is n times the said second sampling rate S2.

Claims

1. A processor for processing a digital audio signal, comprising:

a Delta Sigma Modulator for processing said digital audio signal as a 1-bit signal at a first sampling rate S1 on the basis of a set of coefficients generated from a set of signal parameters;

a plurality of manually adjustable controls for setting said set of signal parameters;

reading means for reading the signal parameters set by said plurality of manually adjustable controls at a second sampling rate S2;

wherein the first sampling rate S1 is at least n times the second sampling rate S2;

coefficient generating means for generating, in n increments, coefficients corresponding to changes in the read signal parameters and supplying the incrementally generated coefficients to the Delta Sigma Modulator at the first sampling rate S1;

whereby adjustments to the set of signal parameters are smoothly applied by the processor.

2. The processor according to claim 1, wherein the Delta Sigma Modulator is configured as an n-th order filter for processing said 1-bit signal.

3. The processor according to claim 1, wherein a plurality of digital input signals are input to the Delta Sigma Modulator for mixing on the basis of the set of coefficients.

4. The processor according to claim 1, wherein the coefficient generating means comprises a first store for storing the incrementally generated coefficients, means for accumulating the incrementally generated coefficients as each increment is supplied to the Delta Sigma Modulator;

and a second store for storing the accumulated coefficients.