Tracking and control of prefetch data in a PCI bus system

• US 6,578,102 B1
• Filed: 04/18/2000
• Issued: 06/10/2003
• Est. Priority Date: 04/18/2000
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Batchelor, Gary William, Benhase, Michael Thomas
• Primary Examiner(s): Myers, Paul R.
• Application Number:
  US09/551,862
• Time in Patent Office: 1,148 Days
• Field of Search: 711/201, 711/105, 710/52, 710/311, 710/308, 710/310
• US Class Current: 710/310
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

A system and method track and control the prefetching of blocks of a data stream in a PCI bus system, avoiding unnecessary prefetches. The data stream is grouped into major blocks which comprise a fixed plurality of contiguous blocks. A prefetch buffer stores the blocks of data prefetched from a PCI data source for transfer to a requester. First and second associated prefetch count storage locations store first and second counts initialized by prefetch initialization logic. The first count represents the number of blocks of data of a major block of the data, and the second count represents the total number of the blocks of the data stream to be prefetched, less the initialized number of blocks of the first count. As each block of data is prefetched, a prefetch counter decrements the first count by a number representing the block of data. As the prefetch counter decrements the first count to zero, prefetch count logic stops the prefetch, allowing completion of the transfer of the prefetched data to the data destination. Thus, the second count represents the next remaining number of blocks to be prefetched, and the requester can rotate to a different read request at the end of a major block, knowing the next major block will not be prefetched until requested.

Claims

1. In a PCI bus system for transferring data in the form of data streams comprising a plurality of contiguous blocks, said PCI bus system having a plurality of PCI busses, at least one PCI data destination coupled to a first of said plurality of PCI busses, at least one PCI data source coupled to a second of said plurality of PCI busses, and a prefetch buffer for storing said blocks of said data prefetched from said PCI data source associated as one of said data streams in response to a read command, said blocks of said data stream stored at said prefetch buffer for transfer to said data destination, said contiguous blocks of data capable of being grouped into major blocks comprising a fixed plurality of said contiguous blocks, a method for tracking and controlling said prefetching of said blocks of said data stream stored at said prefetch buffer, comprising the steps of:

initializing a first count representing the number of said blocks of data comprising up to a major block of said data, and no more than the total number of said blocks of said data stream;

setting a second count representing the total number of said blocks of said data stream to be prefetched and stored in said prefetch buffer, less said initialized number of blocks of said first count;

upon prefetching and storing each said block of data at said prefetch buffer, decrementing said first count by a number representing said block of data; and

upon said first count decrementing step decrementing to zero, stopping said prefetch and allowing completion of said transfer of said prefetched stored data to said data destination, whereby said second count represents the next remaining number of said blocks to be prefetched, stored and transferred.

2. The method of claim 1, additionally comprising the steps of:

upon said completion of said transfer of said prefetched stored data to said data destination, refreshing said first count representing the number of said blocks of data comprising up to a major block of said data, and no more than said remaining second count;

decrementing said second count by said first count, said second count thereby representing the next remaining number of said blocks to be prefetched and stored; and

again conducting said first count decrementing step and said prefetch stopping step.

3. The method of claim 2, wherein said data stream is arranged to have address boundaries between each of said major blocks, and wherein said first count initializing step comprises initializing said first count representing the number of said blocks of data to one of said major block address boundaries.

4. The method of claim 1, wherein said data stream has address boundaries between each of said blocks, wherein said prefetch data stream has an initial address at other than said block boundary, wherein said first count initialization step includes in said first count said data between said initial address and the first said block boundary, and wherein said prefetch stopping step occurs at a block boundary.

5. The method of claim 1, wherein said PCI bus system comprises a plurality of said PCI data destinations, wherein said prefetch buffer comprises a plurality of parallel buffers, at least one of said plurality of parallel buffers assigned to each of said PCI data destinations, and wherein each of said steps, and said first and said second counts of each of said steps, relate to separate ones of said plurality of parallel buffers, each assigned to one of said PCI data destinations.

6. In a PCI bus system for transferring data in the form of data streams comprising a plurality of contiguous blocks, said PCI bus system having a plurality of PCI busses, at least one PCI data destination coupled to a first of said plurality of PCI busses, at least one PCI data source coupled to a second of said plurality of PCI busses, and a prefetch buffer for storing said blocks of said data prefetched from said PCI data source associated as one of said data streams in response to a read command, said blocks of said data stream stored at said prefetch buffer for transfer to said data destination, said contiguous blocks of data capable of being grouped into major blocks comprising a fixed plurality of said contiguous blocks, a system for tracking and controlling said prefetching of said blocks of said data stream stored at said prefetch buffer, comprising:

a first prefetch count storage location for storing a first prefetch count;

a second prefetch count storage location associated with said first prefetch count storage location, said second prefetch count storage location for storing a second prefetch count;

prefetch initialization logic initializing said first count representing the number of said blocks of data comprising up to a major block of said data, and no more than the total number of said blocks of said data stream, and setting said second count representing the total number of said blocks of said data stream to be prefetched and stored in said prefetch buffer, less said initialized number of blocks of said first count;

a prefetch counter coupled to said first and said second prefetch count storage locations, responsive to said PCI bus system, upon said PCI bus system prefetching and storing each said block of data at said prefetch buffer, decrementing said first count by a number representing said block of data; and

prefetch count logic coupled to said prefetch counter, upon said prefetch counter decrementing said first count to zero, stopping said prefetch and allowing completion of said transfer of said prefetched stored data to said data destination, whereby said second count represents the next remaining number of said blocks to be prefetched, stored and transferred.

7. The system of claim 6, wherein:

said prefetch counter additionally, upon said completion of said transfer of said prefetched stored data to said data destination, refreshes said first count representing the number of said blocks of data comprising up to a major block of said data, and no more than said remaining second count;

decrements said second count by said first count, said second count thereby representing the next remaining number of said blocks to be prefetched and stored; and

, again, upon said PCI bus system prefetching and storing each said block of data at said prefetch buffer, decrementing said first count by a number representing said block of data; and

said prefetch count logic, again, upon said prefetch counter decrementing said first count to zero, stopping said prefetch and allowing completion of said transfer of said prefetched stored data to said data destination.

8. The system of claim 7, wherein said data stream is arranged to have address boundaries between each of said major blocks, and wherein said prefetch initialization logic initializes said first count representing the number of said blocks of data to one of said major block address boundaries.

9. The system of claim 6, wherein said data stream has address boundaries between each of said blocks, wherein said prefetch data stream has an initial address at other than said block boundary, wherein said prefetch initialization logic initializes said first count, including in said first count said data between said initial address and the first said block boundary, and wherein said prefetch count logic stops said prefetch at a block boundary.

10. The system of claim 6, wherein said PCI bus system comprises a plurality of said PCI data destinations, wherein said prefetch buffer comprises a plurality of parallel buffers, at least one of said plurality of parallel buffers assigned to each of said PCI data destinations, and wherein said system additionally comprises said first and said second prefetch count storage locations for each of plurality of parallel buffers assigned to each of said PCI data destinations, and wherein said first and said second counts relate to separate ones of said plurality of parallel buffers, each assigned to one of said PCI data destinations.

11. A PCI bus system for transferring data in the form of data streams comprising a plurality of contiguous blocks, said contiguous blocks of data capable of being grouped into major blocks comprising a fixed plurality of said contiguous blocks, between at least one PCI data source and at least one PCI data destination, prefetching said data from said PCI data source associated as one of said data streams in response to a read command, and for tracking and controlling said prefetching of said blocks of said data stream stored at said prefetch buffer, comprising:

said PCI bus system comprising;

a plurality of PCI busses, said at least one PCI data destination coupled to a first of said plurality of PCI busses, and said at least one PCI data source coupled to a second of said plurality of PCI busses;

a prefetch buffer for storing said blocks of said prefetched data associated as one of said data streams, said blocks of said data stream stored at said prefetch buffer for transfer to said data destination;

a first prefetch count storage location for storing a first prefetch count;

a second prefetch count storage location associated with said first prefetch count storage location, said second prefetch count storage location for storing a second prefetch count;

prefetch initialization logic initializing said first count representing the number of said blocks of data comprising up to a major block of said data, and no more than the total number of said blocks of said data stream, and setting said second count representing the total number of said blocks of said data stream to be prefetched and stored in said prefetch buffer, less said initialized number of blocks of said first count;

a prefetch counter coupled to said first and said second prefetch count storage locations, responsive to said PCI bus system, upon said PCI bus system prefetching and storing each said block of data at said prefetch buffer, decrementing said first count by a number representing said block of data; and

prefetch count logic coupled to said prefetch counter, upon said prefetch counter decrementing said first count to zero, stopping said prefetch and allowing completion of said transfer of said prefetched stored data to said data destination, whereby said second count represents the next remaining number of said blocks to be prefetched, stored and transferred.

12. The system of claim 11, wherein:

said prefetch counter additionally, upon said completion of said transfer of said prefetched stored data to said data destination, refreshes said first count representing the number of said blocks of data comprising up to a major block of said data, and no more than said remaining second count;

decrements said second count by said first count, said second count thereby representing the next remaining number of said blocks to be prefetched and stored; and

, again, upon said PCI bus system prefetching and storing each said block of data at said prefetch buffer, decrementing said first count by a number representing said block of data; and

said prefetch count logic, again, upon said prefetch counter decrementing said first count to zero, stopping said prefetch and allowing completion of said transfer of said prefetched stored data to said data destination.

13. The system of claim 12, wherein said data stream is arranged to have address boundaries between each of said major blocks, and wherein said prefetch initialization logic initializes said first count representing the number of said blocks of data to one of said major block address boundaries.

14. The system of claim 11, wherein said data stream has address boundaries between each of said blocks, wherein said prefetch data stream has an initial address at other than said block boundary, wherein said prefetch initialization logic initializes said first count, including in said first count said data between said initial address and the first said block boundary, and wherein said prefetch count logic stops said prefetch at a block boundary.

15. The system of claim 11, wherein said PCI bus system comprises a plurality of said PCI data destinations, wherein said prefetch buffer comprises a plurality of parallel buffers, at least one of said plurality of parallel buffers assigned to each of said PCI data destinations, and wherein said system additionally comprises said first and said second prefetch count storage locations for each of plurality of parallel buffers assigned to each of said PCI data destinations, and wherein said first and said second counts relate to separate ones of said plurality of parallel buffers, each assigned to one of said PCI data destinations.