Compact PCI backplane and method of data transfer across the compact PCI backplane

• US 6,578,103 B1
• Filed: 02/03/2000
• Issued: 06/10/2003
• Est. Priority Date: 02/03/2000
• Status: Expired due to Term

• Current Assignee: Emerson Network Power Embedded Computing Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Hill, Charles C., Kelly, John H., Wong, Henry
• Primary Examiner(s): Shin, Christopher B.
• Application Number:
  US09/497,563
• Time in Patent Office: 1,223 Days
• Field of Search: 710/100, 710/300, 710/305-317, 439/82-83
• US Class Current: 710/313
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438

Abstract

A method of directly transferring data across a CompactPCI™ backplane (170) via a fully meshed orthogonal network (370). The CompactPCI backplane (170) incorporates a different type connector at its P4 location, in conjunction with a standard family of IEC 61074 connectors at its P1, P2, P3, and P5 locations, to provide high speed data transfer with additional shielding and noise control.

Claims

1. A Compact peripheral component interconnect (CompactPCI) backplane comprising:

N P1 connectors parallel to each other;

N P2 connectors parallel to each other and adjacent to said N P1 connectors;

N P3 connectors parallel to each other and adjacent to said N P2 connectors;

N P4 connectors parallel to each other and adjacent to said N P3 connectors;

N P5 connectors parallel to each other and adjacent to said N P4 connectors;

N channels in each of said N P4 connectors; and

N board receivers;

wherein;

N is an integer greater than two;

said pluralities of P1, P2, P3, and P5 connectors are connectors in a first family;

said plurality of P4 connectors are connectors in a second family different from said first family;

a first one of said N P1 connectors, a first one of said N P2 connectors, a first one of said N P3 connectors, a first one of said N P4 connectors, and a first one of said N P5 connectors form a first one of said N board receivers;

a second one of said N P1 connectors, a second one of said N P2 connectors, a second one of said N P3 connectors, a second one of said N P4 connectors, and a second one of said N P5 connectors form a second one of said N board receivers adjacent to said first one of said N board receivers;

a third one of said N P1 connectors, a third one of said N P2 connectors, a third one of said N P3 connectors, a third one of said N P4 connectors, and a third one of said N P5 connectors form a third one of said N board receivers adjacent to said second of said N board receivers; and

said N channels are interconnected to form an orthogonal network comprising;

a first one of said N channels in said first one of said N board receivers coupled to itself;

a first one of said N channels in said second one of said N board receivers coupled to a second one of said N channels in said first one of said N board receivers;

a first one of said N channels in a third one of said N board receivers coupled to a third one of said N channels in said first one of said N board receivers;

a second one of said N channels in said second one of said N board receivers coupled to itself;

a second one of said N channels in said third one of said N board receivers coupled to a third one of said N channels in said second one of said N board receivers; and

a third one of said N channels in said third one of said N board receivers coupled to itself.

2. The CompactPCI backplane of claim 1 comprising:

said N P4 connectors for data transport between said N board receivers;

a pair of transmit lines in each of said N channels in each of said N P4 connectors;

a pair of receive lines adjacent to said pair of transmit lines in each of said N channels in each of said N P4 connectors;

ground lines adjacent to said pairs of transmit and receive lines in each of said N channels in each of said N P4 connectors;

additional ground lines in each of said N P4 connectors forming a shield row adjacent to said first one of said N channels in each of said N P4 connectors to provide protection for said pairs of transmit and receive lines in each of said N channels in each of said N P4 connectors from interference and noise for high density data transport; and

further ground lines in each of said N P4 connectors forming a shield row adjacent to an Nth one of said N channels in each of said N P4 connectors to provide protection for said pairs of transmit and receive lines in each of said N channels in each of said N P4 connectors from interference and noise for high density data transport;

wherein;

said ground lines of said first one of said N channels in each of said N P4 connectors and said ground lines of said second one of said N channels in each of said N P4 connectors form an electrical shield around said pairs of transmit and receive lines in said first one of said N channels in each of said N P4 connectors.