Dual power switching network system for isolating between different power supplies and applying appropriate power supply to a connected peripheral device

• US 6,578,152 B1
• Filed: 02/04/2000
• Issued: 06/10/2003
• Est. Priority Date: 02/04/2000
• Status: Expired due to Term

• Current Assignee: Liberty Patents LLC
• Original Assignee: Iomega Corporation (Dell Technologies Inc.)
• Inventors: Burnside, Michael C.
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): DU, THUAN N
• Application Number:
  US09/497,380
• Time in Patent Office: 1,222 Days
• Field of Search: 713/300, 713/323, 713/324, 713/330, 713/340, 710/62, 710/63, 320/116, 326/34, 326/49, 327/543, 327/546
• US Class Current: 713/300
• CPC Class Codes: G06F 1/263 Arrangements for using multiple switchable power supplies, e.g. battery and AC G06F1/30 takes precedence
• CPC Class Codes: G06F 1/266 Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips

Abstract

In a computer system in which a peripheral device is connected to a host computer through two busses each of which has a power supply, a power switching network turns first and second solid state switching devices (FET'"'"'s) on and off to supply power to the drive. The body diodes of the FET'"'"'s isolate one power supply from the other and supply power to a controller which turns the FET'"'"'s on and off. A time constant circuit turns an FET on gradually and a resistor connected between the gate and source of each FET provide enough voltage to turn the FET off if the bus carries a sleep mode signal.

Claims

1. A computer system comprising:

at least one peripheral device;

first and second buses having first and second power supplies, said first and second busses being connected to said peripheral devices by connectors in a common housing; and

a power switching network including;

first and second solid state switching devices, said first power supply being connected to said peripheral device through said first and second switching devices, said second power supply being connected directly to said peripheral device when said second bus is connected to said peripheral device; and

a controller for turning said first and second switching devices on and off.

2. The computer system recited in claim 1 wherein said controller turns said switching devices on when said second bus is not connected to said peripheral device.

3. The computer system recited in claim 1 wherein said switching devices are first and second field effect transistors (FET'"'"'s) having an inherent body diode.

4. The computer system recited in claim 3 wherein said second FET is connected so that its body diode isolate said first power supply from said second power supply when said second power supply is connected to said peripheral device.

5. The computer system recited in claim 3 wherein said first FET is connected so that its body diode supplies power from said first power supply to said controller.

6. The computer system recited in claim 3 wherein said second FET is connected so that its body diode supplies power from said second power supply to said controller.

7. The computer system recited in claim 3 wherein said FET'"'"'s have a gate which controls current supplied to said peripheral device further comprising:

a time constant circuit on the gate of said second FET to turn said second FET on gradually to limit the current supplied to said peripheral device when said second FET is turned on.

8. The computer system recited in claim 4 wherein said transistors have a gate which controls current supplied to said peripheral device further comprising;

a resistor connected between the gate and the source of each FET, said resistor providing enough voltage to turn the respective FET'"'"'s off if said first bus carries a signal that indicates a sleep mode for said peripheral device.