Data processing system with adjustable clocks for partitioned synchronous interfaces
First Claim
1. A data processing system comprising:
- a. a plurality of processing components, each connected to at least one other of said processing components;
b. a plurality of clock sources, each providing a clock signal;
c. a plurality of controllers associated with each of said processing components;
d. a plurality of clock select registers, each providing a clock select signal; and
e. a plurality of multiplexers, each connected to said plurality of clock sources, to two or more of said plurality of controllers, and to one of said clock select registers, each of said multiplexers providing as an output to said two or more of said plurality of controllers one of said clock signals in response to a clock select signal provided by said one clock select register.
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Abstract
A data processing system (20) having a synchronous interface and partitioned clock and I/O logic controller structure. The system includes a plurality of processing components (22), each having a plurality of I/O logic controllers (24). In addition, the system includes a plurality of clock sources (30) for providing clock signals and a plurality of multiplexers (36) connected to said plurality of clock sources and to at least two of said I/O logic controllers. The clock signals differ from one another in frequency or in skew, i.e., time delay. By appropriate control of clock select registers connected to the plurality of multiplexers, one of the plurality of clock signals from the clock sources may be provided to the two or more I/O logic controllers connected to a given multiplexer. This permits different groups of I/O logic controllers to receive different clock signals in parallel. As a consequence, the signal interface for the system is partitioned into multiple group with each group controlled by a separate clock.
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Citations
14 Claims
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1. A data processing system comprising:
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a. a plurality of processing components, each connected to at least one other of said processing components;
b. a plurality of clock sources, each providing a clock signal;
c. a plurality of controllers associated with each of said processing components;
d. a plurality of clock select registers, each providing a clock select signal; and
e. a plurality of multiplexers, each connected to said plurality of clock sources, to two or more of said plurality of controllers, and to one of said clock select registers, each of said multiplexers providing as an output to said two or more of said plurality of controllers one of said clock signals in response to a clock select signal provided by said one clock select register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of providing clock signals in a data processing system having a plurality of processing components, each of the processing components including a plurality of pins for controlling input and output of data, and a plurality of controllers associated with the processing components, the method comprising the steps of
a. providing a plurality of different clock signals; -
b. selecting one of said plurality of clock signals for each of said plurality of controllers; and
c. providing said selected ones of said plurality of clock signals to said plurality of controllers in parallel and assigning selected ones of said plurality of pins to associated ones of said plurality of processing components.
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Specification