Method of making electronics package with specific areas having low coefficient of thermal expansion

• US 6,579,747 B1
• Filed: 08/15/2002
• Issued: 06/17/2003
• Est. Priority Date: 02/21/2002
• Status: Expired due to Term

• Current Assignee: Jon Zuo
• Original Assignee: Jon Zuo
• Inventors: Zuo, Jon
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, LONG K
• Application Number:
  US10/219,731
• Time in Patent Office: 306 Days
• Field of Search: 438/22, 438/24, 438/117, 438/122-127, 257/81, 257/99, 257/177-181, 257/584, 257/625, 257/675, 257/688, 257/689, 257/705-707, 257/712-722, 257/796
• US Class Current: 438/122
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/3735 Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/427 Cooling by change of state, e.g. use of heat pipes by liquefied gas H01L23/445
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

Method of making semiconductor package including at least one semiconductor chip disposed within a housing, the housing including a lid which overlies the at least one semiconductor chip and a heat-dissipating device coupled to the housing, the heat-dissipating device including at least one area formed of a material with a low coefficient of thermal expansion.

Claims

1. A method for cooling a heat-producing element, comprising steps of:

brazing a heat-dissipating element to a portion of a housing in a vicinity of the heat-producing element, said heat-dissipating element comprising at least one plate formed of a material with a coefficient of thermal expansion that is intermediate of the coefficients of thermal expansion of said at least one semiconductor chip and a remainder of said housing.

2. A method for manufacturing a heat pipe assembly, comprising steps of:

forming a heat pipe assembly housing with at least one plate formed of a material with a coefficient of thermal expansion that is intermediate of the coefficients of thermal expansion of said at least one semiconductor chip and a remainder of said housing.