Method for depositing a two-layer diffusion barrier

• US 6,579,786 B2
• Filed: 11/19/2001
• Issued: 06/17/2003
• Est. Priority Date: 05/17/1999
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Ruf, Alexander, Schmidbauer, Sven
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Soward, Ida M.
• Application Number:
  US09/992,977
• Publication Number:
  US 20020086527A1
• Time in Patent Office: 575 Days
• Field of Search: 438/618, 438/584, 438/643, 438/652, 438/682, 438/685
• US Class Current: 438/618
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric

Abstract

A method for depositing a two-layer diffusion barrier on a semiconductor wafer consisting of a TaN layer and a Ta layer serving as a carrier layer for copper interconnects. The TaN layer is inventively deposited at temperatures above 200° C. in a first step, and the Ta layer is deposited in a second step while cooling the semiconductor wafer to a temperature below 50° C.

Claims

1. A method for depositing a two-layer diffusion barrier on a semiconductor wafer, which comprises:

providing a two-layer diffusion barrier on a semiconductor wafer;

providing the diffusion barrier with a bottom TaN layer and an overlying Ta layer serving as a carrier layer for interconnects; and

depositing the TaN layer in a high-temperature deposition step with a semiconductor wafer temperature above 200°

C., and subsequently depositing the Ta layer in a low-temperature deposition step with the semiconductor wafer temperature below 50°

C.

2. The method according to claim 1, which comprises providing the carrier layer for copper interconnects.

3. The method according to claim 1, wherein the low-temperature deposition step is performed at approximately 25°

C.

4. The method according to claim 1, wherein the step of depositing the Ta layer is performed while cooling the semiconductor wafer to a temperature below 50°

C.

5. The method according to claim 1, which comprises:

performing the steps of depositing the TaN layer and depositing the Ta layer a PVD deposition apparatus; and

performing the step of depositing the TaN layer in a nitrogen atmosphere.

6. The method according to claim 1, which comprises:

performing the step of depositing the TaN layer in a PVD chamber;

depositing the Ta layer in the PVD chamber;

following a degasifying and a precleaning step, when the semiconductor wafer is at a temperature of 200-300°

C., placing the semiconductor wafer in the PVD chamber on an electrostatic chuck, which has been tempered to approximately 25°

C., without clamping the semiconductor wafer on the chuck, and depositing the TaN layer in a nitrogen atmosphere;

after depositing the TaN layer, pumping out excess nitrogen while clamping the semiconductor wafer on the electrostatic chuck; and

depositing the Ta layer in a nitrogen-poor atmosphere while cooling the semiconductor wafer to a low temperature.

7. The method according to claim 1, which comprises:

subsequent to a degasifying and a precleaning step, when the semiconductor wafer has a temperature of 200-300°

C., placing the semiconductor wafer in a first PVD chamber and clamping the semiconductor wafer on an electrostatic chuck that has been tempered to approximately 250-300°

C.; and

subsequently

depositing the TaN layer in a nitrogen atmosphere in the first PVD chamber;

clamping the semiconductor wafer on another electrostatic chuck that has been tempered to a temperature below 50°

C.; and

depositing the Ta layer while cooling the semiconductor wafer to the temperature of the other electrostatic chuck.

8. The method according to claim 1, which comprises after depositing the Ta layer in the low-temperature deposition step, coating the semiconductor wafer with a copper start layer in a chamber selected from the group consisting of a CU-PVD chamber and a CVD chamber.