Multigate semiconductor device with vertical channel current and method of fabrication

• US 6,580,124 B1
• Filed: 08/14/2000
• Issued: 06/17/2003
• Est. Priority Date: 08/14/2000
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Cleeves, James M., Subramanian, Vivek
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US09/639,577
• Time in Patent Office: 1,037 Days
• Field of Search: 257/331, 257/316, 257/324, 257/325, 257/390, 257/391, 257/392, 257/401
• US Class Current: 257/331
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 2211/5611 Multilevel memory cell with more than one control gate
• CPC Class Codes: G11C 2211/5612 Multilevel memory cell with more than one floating gate
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The present invention is a multibit nonvolatile memory and its method of fabrication. According to the present invention a silicon channel body having a first and second channel surface is formed. A charge storage medium is formed adjacent to the first channel surface and a second charge storage medium is formed adjacent to the second channel surface. A first control gate is formed adjacent to the first charge storage medium adjacent to the first channel surface and a second control gate is formed adjacent to the second charge storage medium adjacent to the second surface.

Claims

1. A multibit nonvolatile pillar memory comprising:

a pillar comprising;

a first source/drain region of a first conductivity type;

a channel region of a second conductivity type different from the first conductivity type formed on the first source/drain region;

a second source/drain region of the first conductivity type formed on the channel region;

wherein said first source/drain region, said channel region, and said second source/drain region are in alignment and wherein said pillar has a first face and a second face opposite said first face, a third face adjacent to said first face and a fourth face opposite said third face;

a charge storage medium comprising nanocrystals formed adjacent to each of said first, second, third and forth face of said pillar;

a first control gate adjacent to said charge storage medium adjacent to said first face;

a second control gate adjacent to said charge storage medium adjacent to said second face;

a third control gate adjacent to said charge storage medium adjacent to said third face; and

a fourth control gate adjacent to said charge storage medium adjacent to said fourth face.

3. The memory of claim 1 wherein the channel region of said first face and the channel region of said third face have a different doping density.

2. A multibit nonvolatile pillar memory comprising:

a pillar comprising;

a first source/drain region of a first conductivity type;

a channel region of a second conductivity type different from the first conductivity type formed on the first source/drain region;

a second source/drain region of the first conductivity type formed on the channel region;

wherein said first source/drain region, said channel region, and said second source/drain region are in alignment and wherein said pillar has a first face and a second face opposite said first face, a third face adjacent to said first face and a fourth face opposite said third face;

a charge storage medium formed adjacent to each of said first, second, third and forth face of said pillar;

a first control gate adjacent to said charge storage medium adjacent to said first face;

a second control gate adjacent to said charge storage medium adjacent to said second face;

a third control gate adjacent to said charge storage medium adjacent to said third face; and

a fourth control gate adjacent to said charge storage medium adjacent to said fourth face; and

wherein said charge storage medium is an oxide with H+ ions therein.

4. A multibit nonvolatile pillar memory comprising:

a pillar comprising;

a first source/drain region;

a channel region formed on the first source/drain region;

second source/drain region formed on the channel region;

wherein said first source/drain region, said channel region, and said second source/drain region are in alignment and wherein said pillar has a first face

and a second face opposite said first face, a third face adjacent to said first face and a fourth face opposite said third face;

a charge storage medium formed adjacent to each of said first, second, third and forth face of said pillar;

a first control gate adjacent to said charge storage medium adjacent to said first face;

a second control gate adjacent to said charge storage medium adjacent to said second face;

a third control gate adjacent to said charge storage medium adjacent to said third face;

a fourth control gate adjacent to said charge storage medium adjacent to said fourth face; and

wherein the channel region of said first face and the channel region of said third face have a different doping density; and

the charge storage medium comprises nanocrystals.

5. The memory of claim 4 wherein the channel region of said first face, the channel region of said second face, the channel region of said third face, and the channel region of said fourth face each have a different doping density.

6. A multibit nonvolatile memory comprising:

a first source/drain region of a first conductivity type;

a channel region of a second conductivity type different from the first conductivity type having a first, a second and a third channel surface formed on said first source/drain region,

a second source/drain region of the first conductivity type on said channel region;

a first charge storage medium adjacent to said first channel surface, a second charge storage medium adjacent to said second channel surface, and a third charge storage medium adjacent to said third channel surface, wherein the first, the second and the third charge storage medium comprise nanocrystals;

a first control gate adjacent to said first charge storage medium adjacent to said first channel surface;

a second control gate adjacent to said second charge storage medium adjacent to said second channel surface; and

a third control gate adjacent to said third charge storage medium adjacent to said third channel surface.

8. The memory of claim 6 wherein a first portion of the channel region adjacent to said first surface and a second portion of the channel region adjacent to second surface have a different doping density.

9. The memory of claim 6 further comprising a fourth charge storage medium adjacent to a fourth surface of said channel region and a fourth control gate adjacent to said fourth charge storage medium.

10. The memory of claim 9 wherein a first portion of the channel region adjacent to said first surface, a second portion of the channel region adjacent to said second surface, a third portion of the channel region adjacent to said third surface, and a fourth portion of the channel region adjacent to said fourth surface each have a different doping density.

11. The memory of claim 6 wherein said first, said second and said third control gates are independently controllable.

7. A multibit nonvolatile memory comprising:

a first source/drain region of a first conductivity type;

a channel region of a second conductivity type different from the first conductivity type having a first, a second and a third channel surface formed on said first source/drain region,

a second source/drain region of the first conductivity type on said channel region;

a first charge storage medium adjacent to said first channel surface, a second charge storage medium adjacent to said second channel surface, and a third charge storage medium adjacent to said third channel surface;

a first control gate adjacent to said first charge storage medium adjacent to said first channel surface;

a second control gate adjacent to said second charge storage medium adjacent to said second channel surface; and

a third control gate adjacent to said third charge storage medium adjacent to said third channel surface; and

wherein said first, second and third charge storage medium is an oxide with H+ ions therein.

12. A multibit nonvolatile pillar memory comprising:

a pillar comprising;

a first source/drain region;

a channel region formed on the first source/drain region;

a second source/drain region formed on the channel region;

wherein said first source/drain region, said channel region, and said second source/drain region are in alignment and wherein said pillar has a first face and a second face opposite said first face, a third face adjacent to said first face and a fourth face opposite said third face;

a charge storage medium formed adjacent to each of said first, second, third and forth face of said pillar;

a first control gate adjacent to said charge storage medium adjacent to said first face;

a second control gate adjacent to said charge storage medium adjacent to said second face;

a third control gate adjacent to said charge storage medium adjacent to said third face;

a fourth control gate adjacent to said charge storage medium adjacent to said fourth face; and

wherein the channel region of said first face and the channel region of said third face have a different doping density; and

said charge storage medium comprises an oxide with H+ ions therein.

13. A multibit nonvolatile memory comprising:

a first source/drain region;

a channel region having a first and a second channel surface formed on said first source/drain region, wherein a first portion of the channel region adjacent to said first surface, and a second portion of the channel region adjacent to second surface have a different doping density;

a second source/drain region on said channel region;

a first charge storage medium adjacent to said first channel surface and a second charge storage medium adjacent to said second channel surface, wherein the first and the second charge storage medium comprise nanocrystals or an oxide with H+ ions therein;

a first control gate adjacent to said first charge storage medium adjacent to said first channel surface; and

a second control gate adjacent to said second charge storage medium adjacent to said second channel surface.

14. The memory of claim 13 further comprising:

a third charge storage medium adjacent to a third surface of said channel region and a third control gate adjacent to said third charge storage medium; and

a fourth charge storage medium adjacent to a fourth surface of said channel region and a fourth control gate adjacent to said fourth charge storage medium.

15. The memory of claim 14 wherein the third and the fourth charge storage medium comprise nanocrystals or an oxide with H+ ions therein.

16. The memory of claim 14 wherein the first portion of the channel region adjacent to said first surface, the second portion of the channel region adjacent to said second surface, a third portion of the channel region adjacent to said third surface, and a fourth portion of the channel region adjacent to said fourth surface each have a different doping density.

17. The memory of claim 13 wherein said first and said second control gates are independently controllable.

18. The memory of claim 13 wherein the first charge storage medium and the second charge storage medium comprise nanocrystals.

19. The memory of claim 13 wherein the first charge storage medium and the second charge storage medium comprise an oxide with H+ ions therein.