Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction

• US 6,580,154 B2
• Filed: 05/08/2001
• Issued: 06/17/2003
• Est. Priority Date: 08/31/1999
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P., Reinberg, Alan R.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Dickey, Thomas L
• Application Number:
  US09/850,764
• Publication Number:
  US 20010026006A1
• Time in Patent Office: 770 Days
• Field of Search: 257/206-208, 257/210, 257/288, 257/296, 257/343, 257/396-397, 257/521, 257/527, 257/627, 257/628
• US Class Current: 257/627
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: Y10S 438/973 Substrate orientation

Abstract

Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure'"'"'s channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Embodiments of a method of forming an integrated circuit include forming a trench in a silicon wafer. A trench wall of the trench has a (110) crystal plane orientation. A semiconductor device is also formed lateral to the trench wall such that the semiconductor device is capable of conducting an electrical current in a <110> direction. One method of the present invention provides for forming an integrated circuit. One method includes forming an integrated circuit including an array of MOSFETs and another method includes forming an integrated circuit including a number of lateral transistors. The present invention also includes structures as well as systems incorporating such structures all formed according to the methods provided in this application.

Claims

1. A semiconductor device comprising:

a first conductive region of a first type in a trench of a silicon wafer such that the first conductive region of the first type is lateral to a trench wall of the trench, wherein the trench wall has a (110) crystal plane orientation;

a second conductive region of the first type in the trench such that the second conductive region of the first type is lateral to the trench wall; and

a conductive region of a second type in the trench such that the conductive region of the second type is lateral to the trench wall and between the first and second conductive regions of the first type, and wherein an electrical current is capable of flowing between the first and second conductive region of the first type in a <

110>

direction.

2. The semiconductor device of claim 1, wherein the conductive region of the second type includes a channel of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device.

3. The semiconductor device of claim 1, wherein the first type is an p-type semiconductor region.

4. The semiconductor device of claim 1, wherein the second type is an n-type semiconductor region.

5. The semiconductor device of claim 1, wherein the silicon wafer has a top surface having a (100) crystal plane orientation.

6. A semiconductor device, comprising:

an array of transistors formed laterally on a trench wall, each transistor including;

a first conductive region formed in a first portion of the trench wall;

a second conductive region formed in a second portion of the trench wall;

a third conductive region in a third portion of the trench wall between the first and second conductive regions; and

wherein an electrical current is capable of flowing between the first conductive region and the second conductive region in a <

110>

direction.

7. The semiconductor device of claim 6, wherein the first conductive region and the second conductive region are of a first type and the third conductive region is of a second type.

8. The semiconductor device of claim 7, wherein the first type is one of a p-type or an n-type semiconductor and the second type is an opposite type semiconductor.

9. A semiconductor device, comprising:

at least one trench formed in a silicon wafer;

at least one first conductive region formed laterally in a sidewall of the at least one trench;

at least one second conductive region formed laterally in a sidewall of the at least one trench;

at least one third conductive region in a sidewall of the at least one trench between the at least one first conductive region and the at least one second conductive region; and

wherein the sidewall of the at least one trench has a (110) crystal plane orientation.

10. The semiconductor device of claim 9, wherein the at least one first region and the at least one second region are each one of a p-type or an n-type semiconductor material and the at least one third conductive region is an opposite type semiconductor material.

11. A semiconductor device, comprising:

at least one trench formed in a silicon wafer;

at least one first conductive region formed laterally in a sidewall of the at least one trench;

at least one second conductive region formed laterally in a sidewall of the at least one trench;

at least one third conductive region in a sidewall of the at least one trench between the at least one first conductive region and the at least one second conductive region; and

wherein an electrical current is capable of flowing in a <

110>

direction between the at least one first conductive region and the at least one second conductive region.

12. A semiconductor device, comprising:

a trench formed in a surface of a wafer;

a transistor formed laterally in a sidewall of the trench parallel to the surface of the wafer; and

wherein the sidewall of the trench has a (110) crystalline plane orientation.

13. The semiconductor device of claim 12, further comprising a word line formed in the trench and coupled to a gate of the transistor.

14. A semiconductor device, comprising:

a trench formed in a surface of a wafer;

a transistor formed laterally in a sidewall of the trench parallel to the surface of the wafer, wherein the transistor comprises;

a first conductive region formed lateral to the sidewall;

a second conductive region formed lateral to the sidewall; and

a third conductive region formed lateral to the sidewall and between the first and second conductive regions, wherein an electrical current is capable of flowing between the first and second conductive regions in a <

110>

direction.

15. A semiconductor device, comprising:

a plurality of trenches formed in a surface of a wafer;

at least one metal oxide semiconductor field effect transistor (MOSFET) formed laterally in at least one sidewall of each of the plurality of trenches parallel to the surface of the wafer,

wherein the sidewalls of each of the plurality of trenches include a (110) crystalline plane orientation.

16. The semiconductor device of claim 15, further comprising a word line formed in each of the plurality of trenches, each word line being coupled to a gate of each of the MOSFETs formed in respective ones of the plurality of trenches.

17. A semiconductor device comprising:

at least one trench formed in a silicon wafer; and

an array of transistors formed laterally in at least one sidewall of the at least one trench, wherein electric current is capable of flowing through each of the transistors in a <

110>

direction.

18. The semiconductor device of claim 17, wherein the array of transistors are formed parallel to a surface of the silicon wafer.

19. The semiconductor device of claim 17, further comprising a word line formed in the at least one trench and coupled to each of the transistors.

20. A semiconductor device, comprising:

a trench formed in a surface of a silicon wafer, each sidewall of the trench having a (110) crystal plane orientation;

at least one transistor formed laterally in a sidewall of the trench, the at least one transistor including;

a first conductive region formed in the sidewall of the trench,

a second conductive region formed in the sidewall of the trench laterally from the first conductive region, and

a third conductive region formed in the sidewall of the trench between the first and second conductive regions, wherein electrical current is capable of flowing between the first and second conductive regions in a <

110>

direction.

21. The semiconductor device of claim 20, further comprising a word line formed laterally in the trench parallel to the surface of the silicon wafer and coupled to a gate of the at least one transistor.