Multi-property microprocessor with no additional logic overhead to shared pins

• US 6,580,288 B1
• Filed: 09/09/1999
• Issued: 06/17/2003
• Est. Priority Date: 09/09/1999
• Status: Expired due to Term

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Klapproth, Kenneth Douglas
• Primary Examiner(s): CHANG, DANIEL D
• Application Number:
  US09/392,837
• Time in Patent Office: 1,377 Days
• Field of Search: 326/38, 326/39, 326/41, 326/47, 712/38, 375/219, 710/3, 710/12, 710/52
• US Class Current: 326/38
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: H03K 19/1732 by limitation or reduction of the pin/gate ratio for data-processing equipment G06F1/22
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention is embodied in a system and method for sharing input and output pins between a plurality of separate logic circuits coexisting within a single microprocessor such that the microprocessor is capable of assuming the characteristics of a desired logic circuit. The present invention achieves controlled sharing of bidirectional input and output pins without the requirement to use multiplexing logic. Because the pins may be shared among a plurality of logic circuits, a single microchip may be used for completely different purposes by enabling or disabling selected logic circuits. In other words, a single microchip can take on any number of properties by simply enabling one or more logic circuits while disabling other.

Claims

1. A method for implementing a plurality of logic circuits on a microprocessor, comprising:

receiving a control signal;

inverting the control signal;

sharing connections from input and output pins between at least one of the logic circuits of the microprocessor;

selectively connecting the input and output pins to at least one of the logic circuits in response to the control signal; and

selectively disconnecting the input and output pins of at least another one of the logic circuits in response to the inverted control signal thereby enabling the microprocessor to assume predefined properties of the at least one of the logic circuits.

2. The method for sharing input and output pins claim 1 wherein logic circuits are selectively enabled by a control signal.

3. The method for sharing input and output pins of claim 2 wherein the control signal is inverted to disable logic circuits not enabled by the control signal.

4. The method for sharing input and output pins claim 1 wherein logic circuits are selectively disabled by a control signal.

5. The method for sharing input and output pins of claim 1 wherein each input or output pin is used by one enabled logic circuit at a time.

6. The method for sharing input and output pins of claim 1 wherein input or output pins are not addressable by disabled logic circuits.

7. The method for sharing input and output pins of claim 1 wherein the input and output pins are bidirectional, having the capability of acting as either inputs or outputs for at least one of the logic circuits.

8. The method for sharing input and output pins of claim 7 further comprising a plurality of latch devices for controlling whether each pin acts as an input pin or an output pin.

9. A system for implementing a plurality of logic functions on a microprocessor comprising:

a control pin coupled to the microprocessor that receives a control signal;

an inverter coupled to the control pin that inverts the control signal;

a plurality of logic circuits that share connections of input and output pins of the microprocessor;

a gate on each logic circuit that selectively connects the input and output pins of at least one of logic circuit in response to the control signal, and selectively disconnects the input and output pins of at least another one of the logic circuits in response to the inverted control signal to enable the microprocessor to assume predefined properties of the at least one of the logic circuits.

10. The system of claim 9 wherein the input and output pins are bidirectional, having the capability to act as either input pins or as output pins.

11. The system of claim 9 further comprising a plurality latch devices coupled to each input or output pin.

12. The system of claim 11 wherein specific latch devices have the capability to directly receive the control signal from the control pin.

13. The system of claim 11 wherein specific latch devices have the capability to receive an inverted control signal from the inverter.

14. The system of claim 11 wherein latch devices which receive a logical high control signal enable the input and output pins to act as input pins.

15. The system of claim 11 wherein latch devices which receive a logical low control signal enable the input and output pins to act as output pins.

16. The system of claim 11 wherein specific logic circuits of the plurality of logic circuits are coupled to the control pin.

17. The system of claim 16 wherein each logic circuit has the capability to be enabled by a logical high control signal input to the control pin.

18. The system of claim 16 wherein each logic circuit has the capability to be disabled by a logical low control signal input to the control pin.

19. The system of claim 11 wherein specific logic circuits of the plurality of logic circuits are coupled to the inverter.

20. The system of claim 19 wherein each logic circuit has the capability to be disabled by a logical high control signal input to the control pin.

21. A microprocessor having a plurality of separate logic circuits addressed by shared input and output connections, comprising:

a plurality of control signals coupled to at least one control pin; and

a plurality of latch devices coupled to each shared pin that selectively connects the input and output connections of at least one of logic circuit in response to one of the control signals, and selectively disconnects the input and output connections of at least another one of the logic circuits in response to another control signal so that the microprocessor assumes predefined properties of the at least one of the logic circuits.

22. The microprocessor of claim 21 further comprising an inverter coupled to at least one control pin that inverts at least one of the control signals.

23. The microprocessor of claim 22 wherein the inverter is coupled to specific predefined logic circuits.

24. The microprocessor of claim 23 wherein the inverter is coupled to the logic circuit and has the capability to enable the logic circuit with a logical low control signal input to the at least one control pin.

25. The microprocessor of claim 21 wherein the at least one control pin is coupled to specific predefined logic circuits.

26. The microprocessor of claim 25 wherein the at control pin is coupled to the logic circuit and has the capability to enable the logic circuit with a logical high control signal input to the at least one control pin.