Latch circuit, shift register circuit and image display device operated with a low consumption of power

• US 6,580,411 B1
• Filed: 04/27/1999
• Issued: 06/17/2003
• Est. Priority Date: 04/28/1998
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Maeda, Kazuhiro, Kubota, Yasushi, Shiraki, Ichiro, Washio, Hajime, Kaise, Yasuyoshi
• Primary Examiner(s): Hjerpe, Richard
• Assistant Examiner(s): LESPERANCE, JEAN E
• Application Number:
  US09/300,178
• Time in Patent Office: 1,512 Days
• Field of Search: 345/98, 345/99, 345/100, 345/559, 377/64
• US Class Current: 345/98
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 2320/0257 Reduction of after-image effects
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: H03K 3/356121 with synchronous operation H03K3/35613, H03K3/356147 take precedence
• CPC Class Codes: H03K 3/356139 with synchronous operation

Abstract

If a clock signal ck is “H” and an input pulse signal in (first control signal) is “H”, then n-type transistors M15 and M16 are turned on to make an output node/OUT have the GND level. Then, a p-type transistor M12 is turned on to make an output node OUT have a Vcc (16 V) level. Thus, a latch circuit LAT operates as a level shifter circuit when first and second control signals and the clock signal ck are at “H” and operates as a level hold circuit in any other case. Therefore, the shift register circuit constructed of the latch circuit LAT functions as a low-voltage interface, and the input of the clock signal ck is stopped when the latch circuit LAT is inactive, so that the load and the consumption of power of the clock signal line are reduced.

Claims

1. A latch circuit which receives a pulse signal and a clock signal as inputs and outputs the pulse signal in synchronization with the clock signal, wherein one of the clock signal and the pulse signal has an amplitude smaller than the amplitude of the pulse signal outputted from the latch circuit, the latch circuit comprising:

a first p-type transistor and a second p-type transistor, having source electrodes connected to the power potential and gate electrodes connected to drain electrodes of the counterparts;

a first n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor, a drain electrode connected to a ground potential and a gate electrode connected to the drain electrode of the second p-type transistor;

a second n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to the drain electrode of the first p-type transistor;

a third n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor and a gate electrode that receives the pulse signal as an input;

a fourth n-type transistor having a source electrode connected to the drain electrode of the third n-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the clock signal as an input;

a fifth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor and a gate electrode that receives an inverted signal of the pulse signal as an input; and

a sixth n-type transistor having a source electrode connected to the drain electrode of the fifth n-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the clock signal as an input,

whereby the pulse signal is outputted from the drain electrode of the second p-type transistor, and the inverted signal of the pulse signal is outputted from the drain electrode of the first p-type transistor.

2. A latch circuit which receives a pulse signal and a clock signal as inputs and outputs the pulse signal in synchronization with the clock signal, wherein one of the clock signal and the pulse signal has an amplitude smaller than the amplitude of the pulse signal outputted from the latch circuit, the latch circuit comprising:

a first p-type transistor and a second p-type transistor, having source electrodes connected to the power potential and gate electrodes connected to drain electrodes of the counterparts;

a first n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor and a gate electrode connected to the drain electrode of the second p-type transistor;

a seventh n-type transistor having a source electrode connected to the drain electrode of the first n-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives an inverted signal of the clock signal as an input;

a second n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor and a gate electrode connected to the drain electrode of the first p-type transistor;

an eighth n-type transistor having a source electrode connected to the drain electrode of the second n-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the inverted signal of the clock signal as an input;

a third n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor and a gate electrode that receives the pulse signal as an input;

a fourth n-type transistor having a source electrode connected to the drain electrode of the third n-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the clock signal as an input;

a fifth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor and a gate electrode that receives an inverted signal of the pulse signal as an input; and

a sixth n-type transistor having a source electrode connected to the drain electrode of the fifth n-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the clock signal as an input,

whereby the pulse signal is outputted from the drain electrode of the second p-type transistor, and the inverted signal of the pulse signal is outputted from the drain electrode of the first p-type transistor.

3. A latch circuit which receives a pulse signal and a clock signal as inputs and outputs the pulse signal in synchronization with the clock signal, wherein one of the clock signal and the pulse signal has an amplitude smaller than the amplitude of the pulse signal outputted from the latch circuit, the latch circuit comprising:

a first p-type transistor and a second p-type transistor, having source electrodes connected to the power potential and gate electrodes connected to drain electrodes of the counterparts;

a first n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor and a gate electrode connected to the drain electrode of the second p-type transistor;

a second n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor and a gate electrode connected to the drain electrode of the first p-type transistor;

a third n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor and a gate electrode that receives the pulse signal as an input;

a fifth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor and a gate electrode that receives an inverted signal of the pulse signal as an input; and

a ninth n-type transistor having a source electrode connected to the drain electrodes of the third and fifth n-type transistors, a drain electrode connected to the ground potential and a gate electrode that receives the clock signal as an input; and

a tenth n-type transistor having a source electrode connected to the drain electrodes of the first and second n-type transistors, a drain electrode connected to the ground potential and a gate electrode that receives the inverted signal of the clock signal as an input,

whereby the pulse signal is outputted from the drain electrode of the second p-type transistor, and the inverted signal of the pulse signal is outputted from the drain electrode of the first p-type transistor.

4. A latch circuit which receives a pulse signal and a clock signal as inputs and outputs the pulse signal in synchronization with the clock signal, wherein one of the clock signal and the pulse signal has an amplitude smaller than the amplitude of the pulse signal outputted from the latch circuit, the latch circuit comprising:

a first p-type transistor and a second p-type transistor, having source electrodes connected to the power potential and gate electrodes connected to drain electrodes of the counterparts;

a first n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor, a drain electrode connected to a ground potential and a gate electrode connected to the drain electrode of the second p-type transistor;

a second n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to the drain electrode of the first p-type transistor;

a third n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor and a gate electrode that receives the pulse signal as an input;

a fifth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor and a gate electrode that receives an inverted signal of the pulse signal as an input; and

a ninth n-type transistor having a source electrode connected to the drain electrodes of the third and fifth n-type transistors, a drain electrode connected to the ground potential and a gate electrode that receives the clock signal as an input,

whereby the pulse signal is outputted from the drain electrode of the second p-type transistor, and the inverted signal of the pulse signal is outputted from the drain electrode of the first p-type transistor.

5. A latch circuit which receives a pulse signal and a clock signal as inputs and outputs the pulse signal in synchronization with the clock signal, wherein one of the clock signal and the pulse signal has an amplitude smaller than the amplitude of the pulse signal outputted from the latch circuit, the latch circuit being comprised of first and second logical product and non-disjunction circuits,

the logical product circuit section of the first logical product and non-disjunction circuit receiving the clock signal and the pulse signal as inputs, the non-disjunction circuit section of the first logical product and non-disjunction circuit receiving an output signal of the logical product circuit section and an output signal of the second logical product and non-disjunction circuit as inputs,

the logical product circuit section of the second logical product and non-disjunction circuit receiving the clock signal and the inverted signal of the pulse signal as inputs, and the non-disjunction circuit section of the second logical product and non-disjunction circuit receiving an output signal of the logical product circuit section and an output signal of the first logical product and non-disjunction circuit.

6. A latch circuit as claimed in claim 5, wherein the logical product and non-disjunction circuit comprises:

a first p-type transistor and a second p-type transistor having source electrodes connected to the power potential and gate electrodes connected to the drain electrodes of the counterparts;

a first n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the output signal of the other logical product and non-disjunction circuit as an input;

an eleventh n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor and a gate electrode that receives the inverted signal of the clock signal;

a third n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor and a gate electrode that receives the pulse signal as an input;

a fourth n-type transistor having a source electrode connected to the drain electrode of the third n-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the clock signal as an input;

a fifth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor and a gate electrode that receives the inverted signal of the pulse signal as an input; and

a twelfth n-type transistor having a source electrode connected to the drain electrodes of the eleventh and fifth n-type transistors, a drain electrode connected to the ground potential and a gate electrode that receives the inverted signal of the output signal of the other logical product and non-disjunction circuit as an input,

whereby the pulse signal is outputted from the drain electrode of the first p-type transistor, and the inverted signal of the pulse signal is outputted from the drain electrode of the second p-type transistor.

13. A latch circuit as claimed in claim 6, wherein the first, second, third and fifth n-type transistors have a dual-gate structure, and the fourth, sixth, seventh and eighth n-type transistors have a single-gate structure.

14. A latch circuit as claimed in claim 6, wherein the first, second, third and fifth n-type transistors have a channel length longer than the channel length of the fourth, sixth, seventh and eighth n-type transistors.

7. A latch circuit which receives a pulse signal and a clock signal as inputs and outputs the pulse signal in synchronization with the clock signal, wherein one of the clock signal and the pulse signal has an amplitude smaller than the amplitude of the pulse signal outputted from the latch circuit, the latch circuit comprising:

a first non-conjunction circuit that receives the clock signal and the pulse signal as inputs;

a second non-conjunction circuit that receives the clock signal and the inverted signal of the pulse signal as inputs;

a third non-conjunction circuit that receives an output signal of the first non-conjunction circuit and an output signal of a fourth non-conjunction circuit as inputs; and

the fourth non-conjunction circuit that receives an output signal of the second non-conjunction circuit and an output signal of the third non-conjunction circuit as inputs.

8. A latch circuit as claimed in claim 7, wherein the first and second non-conjunction circuits comprises:

a first p-type transistor and a second p-type transistor, having source electrodes connected to the power potential and gate electrodes connected to the drain electrodes of the counterparts;

a third n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor and a gate electrode that receives the pulse signal as an input;

a fourth n-type transistor having a source electrode connected to the drain electrode of the third n-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the clock signal as an input;

a thirteenth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the inverted signal of the pulse signal as an input; and

a fourteenth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the inverted signal of the clock signal as an input,

whereby the output signal of the first non-conjunction circuit is outputted from the drain electrode of the first p-type transistor, and the inverted signal of the output signal is outputted from the drain electrode of the second p-type transistor.

9. A latch circuit which receives a pulse signal and a clock signal as inputs and outputs the pulse signal in synchronization with the clock signal, wherein one of the clock signal and the pulse signal has an amplitude smaller than the amplitude of the pulse signal outputted from the latch circuit, the latch circuit comprising:

first and second p-type transistors having source electrodes connected to the power potential;

third and fourth p-type transistors having source electrodes connected respectively to the drain electrodes of the first and second p-type transistors, and gate electrodes connected to the clock signal;

third and fifth n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fourth p-type transistors, and gate electrodes connected respectively to an input pulse signal and an inverted signal of the input pulse signal;

fourth and sixth n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fifth n-type transistors, gate electrodes connected to the clock signal, and drain electrodes connected to the ground potential; and

first and second n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fourth p-type transistors, gate electrodes connected respectively to the drain electrodes of the fourth and third p-type transistors, and drain electrodes connected to the ground potential,

whereby the output pulse is outputted from the drain electrode of the fourth p-type transistor, and the inverted signal of the output pulse is outputted from the drain electrode of the third p-type transistor.

10. A latch circuit which receives a pulse signal and a clock signal as inputs and outputs the pulse signal in synchronization with the clock signal, wherein one of the clock signal and the pulse signal has an amplitude smaller than the amplitude of the pulse signal outputted from the latch circuit, the latch circuit comprising:

first and second p-type transistors having source electrodes connected to the power potential;

third and fourth p-type transistors having source electrodes connected respectively to the drain electrodes of the first and second p-type transistors, and gate electrodes connected to the clock signal;

third and fifth n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fourth p-type transistors, and gate electrodes connected respectively to an input pulse signal and an inverted signal of the input pulse signal;

fourth and sixth n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fifth n-type transistors, gate electrodes connected to the clock signal, and drain electrodes connected to the ground potential;

first and second n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fourth p-type transistors, and gate electrodes connected respectively to the drain electrodes of the fourth and third p-type transistors; and

seventh and eighth n-type transistors having source electrodes connected respectively to the drain electrodes of the first and second n-type transistors, gate electrodes connected to the inverted signal of the clock signal, and drain electrodes connected to the ground potential,

whereby the output pulse is outputted from the drain electrode of the fourth p-type transistor, and the inverted signal of the output pulse is outputted from the drain electrode of the third p-type transistor.

11. A latch circuit which receives a pulse signal and a clock signal as inputs and outputs the pulse signal in synchronization with the clock signal, wherein one of the clock signal and the pulse signal has an amplitude smaller than the amplitude of the pulse signal outputted from the latch circuit, the latch circuit comprising:

first and second p-type transistors having source electrodes connected to the power potential;

third and fourth p-type transistors having source electrodes connected respectively to the drain electrodes of the first and second p-type transistors, and gate electrodes connected to the clock signal;

fifth and sixth p-type transistors having source electrodes connected respectively to the drain electrodes of the first and second p-type transistors, gate electrodes connected respectively to an input pulse signal and an inverted signal of the input pulse signal, and drain electrodes connected respectively to the drain electrodes of the third and fourth p-type transistors;

third and fifth n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fourth p-type transistors, and gate electrodes connected respectively to the input pulse signal and the inverted signal of the input pulse signal;

fourth and sixth n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fifth n-type transistors, gate electrodes connected to the clock signal, and drain electrodes connected to the ground potential; and

first and second n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fourth p-type transistors, gate electrodes connected respectively to the drain electrodes of the fourth and third p-type transistors, and drain electrodes connected to the ground potential;

whereby the output pulse is outputted from the drain electrode of the fourth p-type transistor, and the inverted signal of the output pulse is outputted from the drain electrode of the third p-type transistor.

12. A latch circuit which receives a pulse signal and a clock signal as inputs and outputs the pulse signal in synchronization with the clock signal, wherein one of the clock signal and the pulse signal has an amplitude smaller than the amplitude of the pulse signal outputted from the latch circuit, the latch circuit comprising:

first and second p-type transistors having source electrodes connected to the power potential;

third and fourth p-type transistors having source electrodes connected respectively to the drain electrodes of the first and second p-type transistors, and gate electrodes connected to the clock signal;

fifth and sixth p-type transistors having source electrodes connected respectively to the drain electrodes of the first and second p-type transistors, gate electrodes connected respectively to an input pulse signal and an inverted signal of the input pulse signal, and drain electrodes connected respectively to the drain electrodes of the third and fourth p-type transistors;

third and fifth n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fourth p-type transistors, and gate electrodes connected respectively to the input pulse signal and the inverted signal of the input pulse signal;

fourth and sixth n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fifth n-type transistors, gate electrodes connected to the clock signal, and drain electrodes connected to the ground potential;

first and second n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fourth p-type transistors, and gate electrodes connected respectively to the drain electrodes of the fourth and third p-type transistors; and

seventh and eighth n-type transistors having source electrodes connected respectively to the drain electrodes of the first and second n-type transistors, gate electrodes connected to an inverted signal of the clock signal, and drain electrodes connected to the ground potential,

whereby the output pulse is outputted from the drain electrode of the fourth p-type transistor, and the inverted signal of the output pulse is outputted from the drain electrode of the third p-type transistor.

15. A shift register circuit having a plurality of latch circuits for transmitting a pulse signal in synchronization with a clock signal,

the latch circuits each internally having a clock signal input control section for executing control to input and stop the supplied clock signal, and

the clock signal having amplitude smaller than the amplitude of the pulse, wherein

the clock signal input control section is comprised of a first clock signal input control section and a second clock signal input control section, and

the latch circuit comprises:

a first p-type transistor and a second p-type transistor having source electrodes connected to a power potential and gate electrodes connected to drain electrodes of the counterparts;

a first n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor, a drain electrode connected to a ground potential and a gate electrode connected to the drain electrode of the second p-type transistor;

a second n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to the drain electrode of the first p-type transistor;

a third n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor and a gate electrode connected to a pulse signal input node;

a fourth n-type transistor having a source electrode connected to the drain electrode of the third n-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to the first clock signal input control section;

a fifth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor and a gate electrode connected to an inverted pulse signal input node; and

a sixth n-type transistor having a source electrode connected to the drain electrode of the fifth n-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to the second clock signal input control section,

whereby the drain electrode of the second p-type transistor is made to serve as a pulse signal output node and the drain electrode of the first p-type transistor is made to serve as an inverted pulse signal output node.

16. A shift register circuit as claimed in claim 15, wherein

the latch circuit comprises:

a first inverter having an input terminal connected to the inverted pulse signal output node; and

a second inverter having an input terminal connected to the pulse signal output node,

whereby the output terminal of the first inverter is made to serve as a new pulse signal output node and the output terminal of the second inverter is made to serve as a new inverted pulse signal output node.

17. A shift register circuit as claimed in claim 15, wherein

the first clock signal input control section is comprised of a switching means for electrically disconnecting the gate electrode of the fourth n-type transistor from the clock signal input node when the latch circuit becomes inactive and a potential fixing means for fixing the potential of the gate electrode of the fourth n-type transistor that is electrically disconnected from the clock signal input node at a specified potential, and

the second clock signal input control section is comprised of a switching means for electrically disconnecting the gate electrode of the sixth n-type transistor from the clock signal input node when the latch circuit becomes inactive and a potential fixing means fixing the potential of the gate electrode of the sixth n-type transistor that is electrically disconnected from the clock signal input node at a specified potential.

18. A shift register circuit as claimed in claim 17, wherein

the switching means of the first clock signal input control section is comprised of a fifteenth n-type transistor having a source electrode connected to the clock signal input node, a drain electrode connected to the gate electrode of the fourth n-type transistor and a gate electrode connected to the pulse signal input node, and

the switching means of the second clock signal input control section is comprised of a sixteenth n-type transistor having a source electrode connected to the clock signal input node, a drain electrode connected to the gate electrode of the sixth n-type transistor and a gate electrode connected to the pulse signal output node.

19. A shift register circuit as claimed in claim 17, wherein

the potential fixing means of the first clock signal input control section is comprised of a seventeenth n-type transistor having a source electrode connected to the gate electrode of the fourth n-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to the power potential, and

the potential fixing means of the second clock signal input control section is comprised of an eighteenth n-type transistor having a source electrode connected to the gate electrode of the sixth n-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to the power potential.

20. A shift register circuit as claimed in claim 17, wherein

the potential fixing means of the first clock signal input control section is comprised of a nineteenth n-type transistor having a source electrode connected to the gate electrode of the fourth n-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to its own source electrode, and

the potential fixing means of the second clock signal input control section is comprised of a twentieth n-type transistor having a source electrode connected to the gate electrode of the sixth n-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to its own source electrode.

21. A shift register circuit as claimed in claim 17, wherein

the potential fixing means of the first clock signal input control section is comprised of a first resistor provided between the gate electrode of the fourth n-type transistor and the ground potential, and

the potential fixing means of the second clock signal input control section is comprised of a second resistor provided between the gate electrode of the sixth n-type transistor and the ground potential.

22. A shift register circuit as claimed in claim 18, wherein

the potential fixing means of the first clock signal input control section is comprised of a twenty-first n-type transistor having a source electrode connected to the gate electrode of the fourth n-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to the inverted pulse signal input node, and

the potential fixing means of the second clock signal input control section is comprised of a twenty-second n-type transistor having a source electrode connected to the gate electrode of the sixth n-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to the inverted pulse signal output node.

23. An active matrix type image display device comprising:

a plurality of data signal lines arranged in a direction of column;

a plurality of scanning signal lines arranged in a direction of row;

a plurality of pixels that are arranged in a matrix form while being placed in positions surrounded by the data signal lines and the scanning signal lines;

a data signal line drive circuit for supplying a video signal to the data signal lines; and

a scanning signal line drive circuit for supplying a scanning signal to the scanning signal lines,

at least one of the data signal line drive circuit and the scanning signal line drive circuit being comprised of the shift register circuit claimed in claim 15.

24. An image display device as claimed in claim 23, wherein

one of the signal line drive circuits is comprised of the shift register circuit claimed in claim 22 and

constructed so as to generate a drive signal for driving the corresponding signal line by means of an output signal that has a narrower pulse width out of the two output signals of the pulse signal and the inverted pulse signal from each latch circuit constituting the shift register circuit.

25. An image display device as claimed in claim 23, comprising:

a level shifter circuit that amplifies the amplitude of a start signal having the same amplitude as that of the clock signal and supplies the resulting signal as the pulse signal to the latch circuit of the first stage in the shift register circuit of the one signal line drive circuit.

26. An image display device as claimed in claim 23, comprising:

a level shifter circuit that amplifies the amplitude of a control signal having the same amplitude as that of the clock signal and supplies the resulting signal to the one signal line drive circuit.

27. An image display device as claimed in claim 23, wherein

the one signal line drive circuit is formed on a substrate identical to that of the pixels.

28. An image display device as claimed in claim 27, wherein

an active element that constitutes each of the one signal line drive circuit and the pixels is a polysilicon thin-film transistor.

29. An image display device as claimed in claim 28, wherein

the polysilicon thin-film transistor is formed on a glass substrate through a process at a temperature of not higher than 600°

C.