Programmable timing generator

• US 6,580,456 B1
• Filed: 11/09/1998
• Issued: 06/17/2003
• Est. Priority Date: 11/16/1997
• Status: Expired due to Term

• Current Assignee: Pictos Technologies Inc. (f/k/a Imperium IP Holdings (Cayman), Ltd.) (Imperium (IP) Holdings Incorporated)
• Original Assignee: Pictos Technologies Inc. (f/k/a Imperium IP Holdings (Cayman), Ltd.) (Imperium (IP) Holdings Incorporated)
• Inventors: Jacobs, William S.
• Primary Examiner(s): Garber, Wendy R.
• Assistant Examiner(s): Ye, Lin
• Application Number:
  US09/188,831
• Time in Patent Office: 1,681 Days
• Field of Search: 348/312, 348/296, 348/222.1, 348/269, 348/298, 348/311, 348/317, 348/320, 348/322, 348/362, 348/364, 377/77, 377/78, 377/60, 327/291, 327/295
• US Class Current: 348/312
• CPC Class Codes: G11C 19/285 Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage
• CPC Class Codes: H04N 25/41 Extracting pixel data from a plurality of image sensors simultaneously picking up an image, e.g. for increasing the field of view by combining the outputs of a plurality of sensors
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 5/781 on disks or drums
• CPC Class Codes: H04N 5/85 on discs or drums
• CPC Class Codes: H04N 5/907 using static stores, e.g. storage tubes or semiconductor memories H04N5/91 takes precedence
• CPC Class Codes: H04N 7/01 Conversion of standards , e.g. involving analogue television standards or digital television standards processed at pixel level

Abstract

A programmable timing generator for a digital imaging system has a first clock generator and a second clock generator. The first clock generator includes a programmable microsequencer and generates a plurality of first clock signals in response to the microsequencer. The second programmable clock generator is responsive to the microsequencer and generates second clock signals. The first clock signals have a lower frequency than the second clock signals. In a typical implementation, the second clock signals are called horizontal clock signals, which are used for clocking rows of pixel data out of a digital image sensor, while the first clock signals are called vertical clock signals that are used for shifting pixel data one position in vertical shift registers in the digital image sensor. The horizontal or vertical clock signals can also be used to control the image capture operation of the digital sensor, with the programmable microsequencer being used to control the image capture exposure time.

Claims

1. A programmable timing generator for use in a digital imaging system that includes an image sensor and image data processing circuitry, comprising:

a first clock generator including a programmable microsequencer, for generating a plurality of first clock signals in response to instructions executed by the microsequencer; and

a second programmable clock generator, responsive to the microsequencer, for generating a plurality of second clock signals, the second programmable clock generator including;

a clock pattern memory operably configured to store at least one clock pattern to output as the second clock signals;

a starting address latch operably connected to the microsequencer to store a starting address of a selected one of the clock patterns stored in the clock pattern memory; and

address generation circuitry operably connected to the starting address latch for generating a sequence of address signals so as to access the selected one of the clock patterns in the clock pattern memory over a predefined number of clock periods;

wherein the first clock signals include a first set of signals coupled to the image sensor to control a first set of image sensor functions and the second clock signals include a second set of signals coupled to the image sensor to control a second set of image sensor functions, wherein a subset of the second set of signals are also coupled to the image data processing circuitry so as to synchronize operation of the image sensor with operation of the image data processing circuitry.

2. The programmable timing generator of claim 1 wherein one of the second clock signals is a pixel clock signal that is coupled to the first clock generator as a master clock signal for driving the programmable microsequencer.

3. The programmable timing generator of claim 2 wherein the first clock generator includes a plurality of latches for generating ones of the plurality of first clock signals, and an instruction memory for storing a clock signal procedure that is executed by the programmable microsequencer, the clock signal procedure including instructions specifying values to load into the latches so as to generate the plurality of first clock signals;

the clock pattern memory stores at least two distinct clock patterns, including one clock pattern to be used while transferring image data from the image sensor to the image data processing circuitry for processing and storage, and at least one other clock pattern; and

the microsequencer, under control of the clock signal procedure, loads the starting address of the selected clock pattern into the starting address latch in accordance with a current mode of operation of the digital imaging system.

4. The programmable timing generator of claim 2, wherein the address generation circuitry includes a pointer latch coupled to the clock pattern memory that stores a current address used to read clock pattern data from the clock pattern memory,

one of the second clock signals is used as a loop signal that causes the starting address stored in the starting address latch to be loaded into the pointer latch, and

the second programmable clock generator repeatedly outputs the selected one of the clock patterns.

5. The programmable timing generator of claim 4, wherein the address generation circuitry in the second programmable clock generator includes an incrementer operably coupled to the pointer latch to increment the current address stored by the pointer latch.

6. The programmable timing generator of claim 5, wherein the incrementer has an input operably connected to receive the current address of the pointer latch and an output, and the address generation circuitry further comprises:

a multiplexor coupled to the starting address latch, the microsequencer, and the output of the incrementer, the multiplexor having a select input operably coupled to one of the second clock signals and an output operably connected to the pointer latch.

7. The programmable timing generator of claim 2, wherein the first clock generator includes:

a loop counter operably connected to the microsequencer for storing and updating a count value; and

a shadow register that stores a value that is loaded into the loop counter upon execution of a corresponding instruction by the microsequencer;

wherein the count value stored in the loop counter is updated in response to the first clock generator receiving the pixel clock; and

the clock signal procedure includes at least one instruction that causes the microsequencer to provide the starting address latch with the starting address of another of the clock patterns stored in the clock pattern memory when the count value generated by loop counter is equal to a predefined loop end value.

8. A digital camera, comprising:

an image sensor for generating image data that is responsive to a plurality of first clock signals and also to a plurality of second clock signals;

an image memory for storing the image data;

signal processing circuitry coupled to the image sensor and the image memory;

a programmable timing generator for use in a digital imaging system, comprising;

a first clock generator including a programmable microsequencer for generating the first clock signals in response to instructions executed by the microsequencer; and

a second programmable clock generator, responsive to the programmable microsequencer, for generating the second clock signals, the first clock signals having a lower frequency than the second clock signals,

wherein one of the plurality of second clock signals is a pixel clock signal coupled to the image sensor and the signal processing circuitry to synchronize transfer of image data from the image sensor to the image memory, and wherein the pixel clock signal is coupled to the first clock generator as a master clock for the programmable microsequencer.

9. The digital camera of claim 8,

the signal processing circuitry including a digital signal processor, wherein the pixel clock signal synchronizes the transfer of the image data from the image sensor to the image memory via the digital signal processor.

10. The digital camera of claim 9,

the signal processing circuitry including an A/D converter, wherein another one of the plurality of second clock signals is an A/D converter clock signal that controls when the A/D converter converts the image data from the image sensor into a digital data signal to be transferred to the digital signal processor.

11. The digital camera of claim 10, wherein

the second programmable clock generator includes:

a clock pattern memory operably configured to store at least one clock pattern to output as the second clock signals;

a starting address latch operably connected to the microsequencer to store a starting address of a selected one of the clock patterns stored in the clock pattern memory; and

address generation circuitry operably connected to the starting address latch to generate a sequence of address signals so as to access the selected one of the clock patterns in the clock pattern memory over a predefined number of clock periods;

the first clock signals include a first set of signals coupled to the image sensor to control a first set of image sensor functions; and

the second clock signals include a second set of signals coupled to the image sensor to control a second set of image sensor functions, wherein a subset of the second set of signals are also coupled to the image data processing circuitry so as to synchronize operation of the image sensor with operation of the image data processing circuitry.

12. The digital camera of claim 11 wherein

the first clock generator includes a plurality of latches for generating ones of the plurality of first clock signals, and an instruction memory for storing a clock signal procedure that is executed by the programmable microsequencer, the clock signal procedure including instructions specifying values to load into the latches so as to generate the plurality of first clock signals;

the clock pattern memory stores at least two distinct clock patterns, including one clock pattern to be used while transferring image data from the image sensor to the image data processing circuitry for processing and storage, and at least one other clock pattern; and

the microsequencer, under control of the clock signal procedure, loads the starting address of the selected clock pattern into the starting address latch in accordance with a current mode of operation of the digital imaging system.

13. The digital camera of claim 11 wherein

the address generation circuitry includes a pointer latch coupled to the clock pattern memory that stores a current address used to read clock pattern data from the clock pattern memory, and

one of the second clock signals is used as a loop signal that causes the starting address stored in the starting address latch to be loaded into the pointer latch, and

the second programmable clock generator repeatedly outputs the selected one of the clock patterns.

14. The digital camera of the claim 13, wherein the address generation circuitry in the second programmable clock generator includes an incrementer operably coupled to the pointer latch to increment the current address stored by the pointer latch.

15. The digital camera of claim 14, wherein the incrementer has an input operably connected to receive the current address of the pointer latch and an output, and the address generation circuitry further comprises:

a multiplexor coupled to the starting address latch, the microsequencer, and the output of the incrementer, the multiplexor having a select input operably coupled to one of the second clock signals and an output operably connected to the pointer latch.

16. The digital camera of claim 12, wherein

the first clock generator includes:

a loop counter operably connected to the microsequencer for storing and updating a count value; and

a shadow register that stores a value that is loaded into the loop counter upon execution of a corresponding instruction by the microsequencer;

wherein the count value stored in the loop counter is updated in response to the first clock generator receiving the pixel clock; and

the clock signal procedure includes at least one instruction that causes the microsequencer to provide the starting address latch with the starting address of another of the clock patterns stored in the clock pattern memory when the count value generated by loop counter is equal to a predefined loop end value.

17. A programmable timing generator for controlling an image sensor in a digital imaging system, comprising:

a vertical clock generator having a programmable microsequencer operably configured to execute a clock signal procedure having a plurality of instructions, the vertical clock generator operably configured to generate a plurality of vertical clock signals in response to at least one of the instructions executed by the microsequencer; and

a horizontal clock generator operably connected to the programmable microsequencer and having;

a clock pattern memory having a plurality of addresses, and operably configured to store a plurality of clock patterns and to selectively output a plurality of horizontal clock signals corresponding to the clock patterns, each clock pattern having a plurality of states, each state of each clock pattern being stored at a different one of the addresses of the clock pattern memory;

a starting address latch operably connected to the microsequencer to store a starting address of a selected one of the clock patterns stored in the clock pattern memory; and

address generation means operably connected to the microsequencer and to the starting address latch for generating a sequence of address signals to access each state of the selected one of the clock patterns stored in the clock pattern memory.

18. The programmable timing generator of claim 17, wherein the address generation means comprises:

a pointer latch operably connected to the clock pattern memory;

an incrementer having an output and an input operably connected to the pointer latch;

a multiplexor having a plurality of inputs operably connected to the starting address latch and the output of the incrementer, the multiplexor having a select input operably connected to the microsequencer and having an output operably connected to the pointer latch,

wherein the pointer latch is operably configured to receive the starting address of the selected one of the clock patterns in response to a load signal present on the select input of the multiplexor.

19. The programmable timing generator of claim 18, wherein the multiplexor has another control input operably connected to one of the horizontal clock signals, and the pointer latch is operably configured to receive an incremented address from the incrementer in response to a loop signal present on the other select input of the multiplexor.