Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks

• US 6,580,638 B2
• Filed: 06/21/2002
• Issued: 06/17/2003
• Est. Priority Date: 02/17/2000
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Conley, Kevin M., Mangan, John S., Craig, Jeffrey G.
• Primary Examiner(s): Lebentritt, Michael S.
• Assistant Examiner(s): Nguyen, Tuan T.
• Application Number:
  US10/176,880
• Publication Number:
  US 20020154543A1
• Time in Patent Office: 361 Days
• Field of Search: 365/185.11, 365/189.04, 365/185.09
• US Class Current: 365/185.11
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/107 Programming all cells in an array, sector or block to the same state prior to flash erasing
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

Claims

1. A method of operating a re-programmable non-volatile memory system having memory cells organized into distinct blocks of simultaneously erasable cells, comprising:

utilizing a first group of said blocks for storing user data and a second group of said blocks for storing information of the characteristics of said first group of blocks,

storing, in individual ones of the first group of said blocks, user data plus characteristics of the user data being written therein but not including characteristics of said first group of blocks, and

storing, in individual ones of the second group of said blocks, a plurality of records of characteristics of a plurality of the first group of blocks but without storing either user data or characteristics of the user data in the second group of blocks.

2. The method of claim 1, wherein storing characteristics of the user data in individual ones of the first group of blocks includes generating redundancy codes from the user data and then separately storing the redundancy codes in the blocks containing the user data from which the redundancy codes were generated.

3. The method of claim 1, wherein storing the plurality of records in individual ones of the second group of said blocks includes generating redundancy codes from records of characteristics of a plurality of the first group of blocks and storing the generated redundancy codes in the same blocks as the records from which they were generated.

4. The method of claim 1, wherein storing, in individual ones of the second group of blocks, records of characteristics of a plurality of the first group of blocks includes storing parameters for use during the programming of user data into the first group of blocks.

5. The method of claim 1, wherein storing, in the second group of blocks, the records of characteristics of the first group of blocks includes storing in individual records an indication of whether a corresponding block within said first group is defective or not, and, if so, storing an address of a substitute block, and, if not, storing instead at least one operating parameter of the corresponding block within said first group.

6. The method of claim 5, wherein storing at least one operating parameter includes storing any of programming, reading, erase or wear characteristics of the corresponding block within the first group.

7. The method of any one of claims 1 or 2-6, wherein the memory cells within at least a plurality of said blocks include charge storage elements that are individually operated with more than two storage states in order to store more than one bit of data per charge storage element.

8. The method of any one of claims 1 or 2-6, wherein the memory cells within the first group of said blocks include charge storage elements that are individually operated with more than two storage states in order to store more than one bit of data per charge storage element, and wherein the memory cells within the second group of blocks include charge storage elements that are individually operated with exactly two storage states in order to store exactly one bit of data per charge storage element.

9. A method of operating a re-programmable non-volatile memory system having a plurality of distinct units of semiconductor memory cells, wherein the memory cells of the individual units are simultaneously erasable, comprising:

utilizing a first group of said units for storing user data and a second group of said units for storing information of a characteristic of the individual units of said first group, the characteristic being at least one of an erase operating parameter, a programming operating parameter or a number of operating cycles,

storing, in the first group of said units, user data without information of the characteristic, and

storing, in the second group of said units, a plurality of records of the characteristic of individual ones of the first group of units but without storing user data in the second group of units.

10. The method of claim 9, wherein storing the plurality of records in the second group of said units includes storing redundancy codes generated from the information of data of the characteristic that is stored therein.

11. The method of claim 9, additionally comprising:

reading a plurality of the records from at least one of the second group of units and storing the read records in a controller memory outside of the non-volatile memory system, and

when accessing one or more of the first group of units to program user data therein or to read user data therefrom, reading from the controller memory those of the records stored therein which contain the characteristic of said one or more of the first group of units being accessed.

12. The method of claim 11, wherein records having the longest time since being read are removed therefrom when a limited capacity of the controller memory requires space to be made for additional records to be stored therein in order to be read when one or more of corresponding units is being accessed from the first group of units.

13. The method of claim 11, wherein, when a plurality of the first group of units with successive addresses are being accessed, an address of a record stored in the controller memory that corresponds to a first of the addressed plurality of the first group of units is calculated and remaining records within the controller memory that correspond to others of the plurality of the first group of units being accessed are addressed by incrementing from one record address to another.

14. The method of any one of claims 9-13, wherein the method is practiced when the memory system is enclosed within a card that is removably connectable to a host system.

15. The method of any one of claims 9-13, wherein charge storage elements within the memory cells of at least some of the plurality of units are individually operated with more than two storage states in order to store more than one bit of data per charge storage element.

16. A method of operating a re-programmable non-volatile memory system having a plurality of distinct units of semiconductor memory cells, wherein the memory cells of the individual units are simultaneously erasable, comprising:

utilizing a first group of said units for storing user data and a second group of said units for storing records of characteristics of the individual units of said first group,

storing, in the first group of said units, user data without the characteristics of the first group of units, and

storing, in the second group of said units, a plurality of said records without user data, wherein said records individually includes an indication of whether a corresponding one of the first group of said units is good or defective, and, if a good indication, further includes data of at least one operating parameter of the corresponding block of the first group, and, if a defective indication, further includes data of an address of another good block without said data of said at least one operating parameter.

17. The method of claim 16, wherein said at least one operating parameter includes at least one of an erase operating parameter, a programming operating parameter or a number of operating cycles.

18. The method of claim 16, wherein storing the plurality of records in the second group of said units includes storing redundancy codes generated from the information of data of the characteristic that is stored therein.

19. The method of any one of claims 16-18, wherein the method is practiced when the memory system is enclosed within a card that is removably connectable to a host system.

20. The method of any one of claims 16-18, wherein charge storage elements within the memory cells of at least some of the plurality of units are individually operated with more than two storage states in order to store more than one bit of data per charge storage element.

21. A memory system, comprising:

at least two non-volatile memory cell arrays formed on at least two respective integrated circuit chips, wherein the memory cells of each of the memory cell arrays are grouped into a number of units of memory cells that are simultaneously erasable and designated to individually store a given quantity of user data, and further wherein the number of such available units is different in individual ones of said at least two memory cell arrays,

a memory controller, and

a record stored in the memory system which contains non-overlapping logical address assignments of the units of each of the memory cell arrays, thereby to allow the controller to determine from a logical address which of the memory arrays a corresponding physical unit lies.

22. The memory system of claim 21, wherein the logical address assignment record is stored within one of said at least two integrated circuit chips.

23. The memory system of claim 21, wherein said at least two integrated circuit chips and the controller are positioned within an enclosed memory card having electrical contacts thereon that match electrical contacts of a socket of a host system, the card thereby being removably connectable with the host.

24. The memory system of claim 21, wherein said at least two integrated circuit chips and the controller are embedded within a host system.

25. The memory system of claim 21, wherein the controller is formed on one of said at least two integrated circuit chips.

26. The memory system of claim 21, wherein the controller is formed on an integrated circuit chip without a non-volatile memory cell array and that is in addition to said at least two integrated circuit chips.

27. A method of manufacturing a memory system, comprising:

installing and interconnecting at least first and second integrated circuit chips that individually include an array of non-volatile memory cells, wherein said at least first and second integrated circuit chips individually contains stored therein a record of at least a number of units of capacity of its memory cell array for storing user data, and

merging the memory array capacity records of each of said at least first and second integrated circuit chips to form a merged record in the array of non-volatile memory cells of said first integrated circuit chip with contiguous ranges of logical memory block addresses assigned to the memory cell arrays of each of the at least first and second integrated circuit chips.

28. The method of claim 27, wherein the number of units of memory capacity for storing user data is different among said at least first and second circuit chips.

29. The method of claim 27, wherein the number of units of memory capacity for storing user data is the same among said at least first and second circuit chips.

30. The method of claim 27, additionally comprising installing said at least first and second circuit chips within an enclosed memory card having electrical contacts thereon for engaging contacts of a connector of a host system.

31. The method of claim 27, additionally comprising embedding said at least first and second circuit chips within a host system.

32. A method of operating a memory system having a controller and memory cells organized into distinct units of a number of simultaneously erasable memory cells that are individually capable of storing a given quantity of data, comprising:

operating the memory system with a plurality of arrays of said memory cells on at least two integrated circuit chips,

storing in one of the memory units of one of the plurality of arrays a record of(1) a number of units that are available in each of said plurality of memory cell arrays for storing user data and (2) non-overlapping ranges of contiguous logical addresses assigned to said number of the user data units of the individual memory cell arrays, and

locating a physical address of a memory cell unit at least in part by accessing the record with a logical address in order to determine one of the plurality of memory cell arrays in which the addressed memory cell unit resides.

33. The method of claim 32, wherein the number of units of memory capacity for storing user data is different among at least two of the plurality of arrays of memory cells.

34. The method of claim 32, wherein said at least two integrated circuit chips are enclosed in a memory card having electrical contacts thereon for engaging contacts of a host connector.

35. The method of claim 32, wherein charge storage elements of the memory cells within at least some of said memory cell units are individually operated with more than two storage states in order to store more than one bit of data per charge storage element.

36. A method of operating a memory system including at least first and second integrated circuit chips individually containing an array of non-volatile memory cells grouped into a number of units of memory cells that are simultaneously erasable, comprising:

utilizing a plurality of the memory cell units on each of the first and second integrated circuit chips for storing user data therein,

storing data of operating parameters in at least one of the memory cell units other than the user data units on each of said first and second integrated chips, the stored data of at least some of the operating parameters being different on the first and second integrated circuit chips, and

controlling operation of the first and second integrated circuit chips in accordance with the data of operating parameters stored on their respective operating parameter units.

37. The method of claim 36, wherein storing data of operating parameters includes storing data of operating voltages.

38. The method of claim 36, wherein storing data of operating parameters includes storing timing data.

39. The method of either of claims 37 or 38, wherein controlling operation of the first and second integrated circuit chips includes utilizing the data of the operating parameters to program user data into the plurality of the memory cell units.

40. The method of either of claims 37 or 38, wherein controlling operation of the first and second integrated circuit chips includes utilizing the data of the operating parameters to read user data from the plurality of the memory cell units.

41. The method of either of claims 37 or 38, wherein controlling operation of the first and second integrated circuit chips includes utilizing the data of the operating parameters to erase the plurality of the memory cell units.

42. The method of either of claims 37 or 38, wherein controlling operation of the first and second integrated circuit chips includes utilizing the data of the operating parameters to scrub the plurality of the memory cell units.

43. A memory system, comprising:

at least two integrated circuit chips that individually contain an array of non-volatile memory cells grouped into a number of units of memory cells that are simultaneously erasable,

a plurality of the memory cell units on each of said at least two integrated circuit chips designated to store user data,

at least one of the memory cell units other than the user data units on each of said at least two integrated chips designated to store characteristics of the integrated circuit chip on which said at least one of the memory cell units resides, said characteristics including parameters for scrubbing user data stored in the user data units of the integrated circuit chip on which said at least one of the memory cell units resides, and

controlling circuits adapted to cause the user data units of each of said at least two integrated circuit chips to be scrubbed in accordance with the scrubbing parameters stored on respective ones of each of said at least two integrated circuit chips.

44. The memory system of claim 43, wherein the controlling circuits are included on a controller integrated circuit chip different from said at least two integrated circuit chips, and wherein said at least two integrated circuit chips and the controller integrated circuit chip are positioned within an enclosed memory card having electrical contacts thereon that match electrical contacts of a socket of a host system, the card thereby being removably connectable with the host.