Low-power organic light emitting diode pixel circuit

• US 6,580,657 B2
• Filed: 01/04/2001
• Issued: 06/17/2003
• Est. Priority Date: 01/04/2001
• Status: Expired due to Term

• Current Assignee: InnoLux Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Sanford, James Lawrence, Schlig, Eugene S.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): HO, TU TU V
• Application Number:
  US09/754,489
• Publication Number:
  US 20020084463A1
• Time in Patent Office: 894 Days
• Field of Search: 257/59, 257/88, 257/93, 345/76, 345/82, 315/169.3, 315/169.1
• US Class Current: 365/230.05
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/0254 Control of polarity reversal in general, other than for liquid crystal displays
• CPC Class Codes: G09G 2310/0256 with the purpose of reversing the voltage across a light emitting or modulating element within a pixel
• CPC Class Codes: G09G 2310/063 Waveforms for resetting the whole screen at once
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 2320/046 Dealing with screen burn-in prevention or compensation of the effects thereof
• CPC Class Codes: G09G 2320/0626 for control of overall brightness
• CPC Class Codes: G09G 2320/0633 by amplitude modulation of the brightness of the illumination source
• CPC Class Codes: G09G 2320/064 by time modulation of the brightness of the illumination source
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2330/022 in absence of operation, e.g. no data being entered during a predetermined time
• CPC Class Codes: G09G 2330/04 Display protection
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3291 in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: H10K 59/00 : Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
• CPC Class Codes: H10K 59/12 : Active-matrix OLED [AMOLED] displays

Abstract

A pixel circuit comprises an organic light emitting diode (OLED), and a static memory for storing data that represents an operational state of the OLED. In alternative embodiments, a pixel circuit may include a complementary metal oxide semiconductor (CMOS) circuit for controlling the OLED, a protection circuit for protecting the CMOS circuit from an over-voltage condition, and a current source with a field effect transistor (FET) having a static gate to source voltage that is greater than a threshold voltage of the FET.

Claims

1. A pixel circuit comprising:

a static memory for storing data that represents an operational state of a pixel;

a first input to enable writing data into said static memory;

a second input to enable reading data from said static memory; and

wherein said static memory comprises;

a first component through which a data signal is coupled to provide a source signal drive current;

a second component having an input for receiving said source signal drive current from said first component, and for being driven to a state to produce at an output thereof an output drive current that represents said stored data; and

a third component having an input coupled to said output of said second component, and an output coupled to said input of said second component, for providing a latch signal drive current, which is less than said source signal drive current and said output drive current of said second component, to thereby maintain said state of said second component after a removal of said source signal.

2. The pixel circuit of claim 1, further comprising a single bit line for inputting a signal that represents said data to, and outputting a signal that represents said data from, said static memory.

3. The pixel circuit of claim 2, wherein said static memory further comprises a fourth component that couples said output of said second component that represents said stored data to said single bit line.

4. The pixel circuit of claim 1,

wherein said pixel circuit comprises a material disposed on a substrate,

wherein said material is selected from the group consisting of crystalline silicon, amorphous silicon, polysilicon, micro crystalline silicon, an organic material and a polymer material, and

wherein said substrate is selected from the group consisting of silicon, glass, plastic, ceramic and sapphire (AL₂O₃).

5. The pixel circuit of claim 1, wherein said pixel comprises an organic light emitting diode (OLED).

6. A display comprising an array of pixel circuits, wherein each of said pixel circuits comprises:

a light emitting device;

a static memory for storing data that represents an operational state of said light emitting device;

a first control input for enabling the writing of data to said static memory;

a second control input for enabling the reading of data from said static memory, wherein said data represents a luminous state of said light emitting device; and

wherein said static memory comprises;

a first component through which a data signal is coupled to provide a source signal drive current;

a second component having an input for receiving said source signal drive current from said first component, and for being driven to a state to produce at an output thereof an output drive current that represents said stored data; and

a third component having an input coupled to said output of said second component, and an output coupled to said input of said second component, for providing a latch signal drive current, which is less than said source signal drive current and said output drive current of said second component, to thereby maintain said state of said second component after a removal of said source signal.

7. The display of claim 6, wherein each of said pixel circuits is addressed by a processor via a memory bus.

8. The display of claim 6, wherein said array is a component of an electronic watch.

9. The display of claim 6, wherein said light emitting device comprises an organic light emitting diode.

10. The display of claim 9, wherein each said OLED comprises an electrode, wherein said OLEDs are separated from one another by a pitch that is uniform throughout said array, and wherein said pixel circuits are separated from one another by a pitch that is not uniform throughout said array.

11. The display of claim 9, further comprising a circuit for simultaneously setting all of said OLEDs to a uniform operation at state.

12. The display of claim 11, wherein said uniform operational state of said OLEDs is OFF, and wherein said display is controlled by a processor that subsequently sets selected individuals of said OLEDs ON.

13. The display of claim 11, wherein said circuit is addressed by a processor via a memory bus.

14. The display of claim 6, further comprising a single bit line for inputting a signal that represents said data to, and outputting a signal that represents said data, from said static memory.

15. The display of claim 14, wherein said static memory further comprises a fourth component that couples said output of said second component that represents said stored data to said single bit line.

16. A static memory cell circuit comprising:

a semiconductor memory cell;

a first control input for writing data into said memory cell;

a second control input for reading data from said memory cell; and

wherein said memory cell comprises;

a first component through which a data signal is coupled to provide a source signal drive current;

a second component having an input for receiving said source signal drive current from said first component, and for being driven to a state to produce at an output thereof an output drive current that represents said written data; and

a third component having an input coupled to said output of said second component, and an output coupled to said input of said second component, for providing a latch signal drive current, which is less than said source signal drive current and said output drive current of said second component, to thereby maintain said state of said second component after a removal of said source signal.

17. The static memory cell circuit of claim 16, further comprising:

a single bit line for writing and reading data to and from said memory cell.

18. The static memory cell circuit of claim 16, further comprising a single bit line for inputting a signal that represents said data to, and outputting a signal that represents said data, from said memory cell.

19. The static memory cell circuit of claim 18, wherein said memory cell further comprises a fourth component that couples said output of said second component that represents said stored data to said single bit line.

20. A static memory comprising:

an array of semiconductor circuits, each semiconductor circuit being capable of storing a bit of data;

a first control input connected to each of said semiconductor circuits for writing data;

a second control input connected to each of said semiconductor circuits for reading data; and

wherein each of said semiconductor circuits comprises;

a first component through which a data signal is coupled to provide a source signal drive current;

a second component having an input for receiving said source signal drive current from said first component, and for being driven to a state to produce at an output thereof an output drive current that represents said stored data; and

a third component having an input coupled to said output of said second component, and an output coupled to said input of said second component, for providing a latch signal drive current, which is less than said source signal drive current and said output drive current of said second component, to thereby maintain said state of said second component after a removal of said source signal.

21. The static memory of claim 20, further comprising separate single bit lines connected to separate ones of said semiconductor circuits.

22. The static memory of claim 21, further comprising a second array of semiconductor circuits with said separate bit lines also being connected to separate ones of the semiconductor circuits of said second array.

23. The static memory of claim 22, further comprising:

a third control input connected to each of the semiconductor circuits of said second array for writing data; and

a fourth control input connected to each of the semiconductor circuit of said second array for reading data.

24. The static memory of claim 20, wherein each of said semiconductor circuits further comprises a light emitting device and said data represents a luminance state thereof.

25. The static memory of claim 20, further comprising a single bit line for inputting a signal that represents said data to, and outputting a signal that represents said data, from one or more of said semiconductor circuits.

26. The static memory of claim 25, wherein each of said semiconductor circuits further comprises a fourth component that couples said output of said second component that represents said stored data to said single bit line.