Frequency translation using optimized switch structures

• US 6,580,902 B1
• Filed: 04/16/1999
• Issued: 06/17/2003
• Est. Priority Date: 10/21/1998
• Status: Expired due to Term

• Current Assignee: ParkerVision, Inc.
• Original Assignee: ParkerVision, Inc.
• Inventors: Cook, Robert W., Bultman, Michael J., Sorrells, David F., Moses, Charley D. Jr., Looke, Richard C.
• Primary Examiner(s): Chin, Vivian
• Assistant Examiner(s): Moore, James K
• Application Number:
  US09/293,095
• Time in Patent Office: 1,523 Days
• Field of Search: 455/313, 455/333, 455/323, 329/361, 329/362, 329/369, 329/358
• US Class Current: 455/333
• CPC Class Codes: H03C 1/62 Modulators in which amplitude of carrier component in output is dependent upon strength of modulating signal, e.g. no carrier output when no modulating signal is present H03C1/28 - H03C1/34, H03C1/46, H03C1/48 take precedence
• CPC Class Codes: H03D 7/00 Transference of modulation from one carrier to another, e.g. frequency-changing H03D9/00, H03D11/00 take precedence; dielectric amplifiers, magnetic amplifiers, parametric amplifiers used as a frequency-changers H03F
• CPC Class Codes: H03D 7/1441 using field-effect transistors H03D7/145 takes precedence
• CPC Class Codes: H03D 7/1475 Subharmonic mixer arrangements
• CPC Class Codes: H04B 1/0025 using a sampling rate lower than twice the highest frequency component of the sampled signal for demodulation of angle-modulated signals H03D3/006
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04B 7/12 Frequency diversity
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 27/00 Modulated-carrier systems
• CPC Class Codes: H04L 27/06 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/12 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/14 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/148 using filters, including PLL-type filters
• CPC Class Codes: H04L 27/156 with demodulation using temporal properties of the received signal, e.g. detecting pulse width
• CPC Class Codes: H04L 27/2672 Frequency domain
• CPC Class Codes: H04L 27/3881 using sampling and digital processing, not including digital systems which imitate heterodyne or homodyne demodulation

Abstract

Methods, systems, and apparatuses for down-converting an electromagnetic (EM) signal by aliasing the EM signal are described herein. Briefly stated, such methods, systems, and apparatuses operate by receiving an EM signal and an aliasing signal having an aliasing rate. The EM signal is aliased according to the aliasing signal to down-convert the EM signal. The term aliasing, as used herein, refers to both down-converting an EM signal by under-sampling the EM signal at an aliasing rate, and down-converting an EM signal by transferring energy from the EM signal at the aliasing rate. In an embodiment, the EM signal is down-converted to an intermediate frequency (IF) signal. In another embodiment, the EM signal is down-converted to a demodulated baseband information signal. In another embodiment, the EM signal is a frequency modulated (FM) signal, which is down-converted to a non-FM signal, such as a phase modulated (PM) signal or an amplitude modulated (AM) signal.

Claims

1. A circuit for down-converting an electromagnetic signal, comprising:

an energy transfer module having a switch module and an energy storage module, said energy transfer module sampling the electromagnetic signal at an energy transfer rate, according to an energy transfer signal, to obtain sampled energy, said sampled energy being stored by said energy storage module, a down-converted signal being generated from said sampled energy, wherein

said energy transfer module further comprises;

transistors coupled together, said transistors having a common first port, a common second port, and a common control port, wherein the electromagnetic signal is accepted at said common first port and said sampled energy is present at said common second port, and further wherein said common control port accepts said energy transfer signal, said energy transfer signal having a control frequency that is substantially equal to said energy transfer rate, and

wherein each of said transistors has a drain, a source, and a gate, and said common first port couples together drains of said transistors, said common second port couples together sources of said transistors, and said common control port couples together gates of said transistors.

2. The circuit of claim 1, wherein each of said transistors is a field effect transistor (FET).

3. The circuit of claim 2, wherein each of said field effect transistors is a p-channel FET.

4. The circuit of claim 2, wherein each of said field effect transistors is an n-channel FET.

5. The circuit of claim 2, wherein all of said field effect transistors are substantially the same size.

6. The circuit of claim 2, wherein at least some of said field effect transistors vary in size.

7. The circuit of claim 1, wherein said energy transfer module comprises twenty or less transistors.

8. The circuit of claim 1, wherein said energy transfer module comprises fourteen or less transistors.

9. A circuit for down-converting an electromagnetic signal, comprising:

an energy transfer module and an energy storage module, said energy transfer module sampling the electromagnetic signal at an energy transfer rate thereby obtaining sampled energy, said sampled energy being stored by said energy storage module, a down-converted signal being obtained from said sampled energy, wherein

said energy transfer module comprises;

first transistors coupled together, said first transistors having a first common first port, a first common second port, and a first common control port,

second transistors coupled together, said second transistors having a second common first port, a second common second port, and a second common control port,

wherein each of said first transistors is an “

n-channel”

transistor and each of said second transistors is a “

p-channel”

transistor, and wherein

said first common first port is coupled to said second common first port to form a common first port, said first common second port is coupled to said second common second port to form a common second port, and said first common control port is coupled to said second common control port to form a common control port,

wherein the electromagnetic signal is accepted at said common first port and said sampled energy is present at said common second port, and further wherein said common control port accepts a control signal, said control signal having a control frequency that is substantially equal to said energy transfer rate.

10. The circuit of claim 9, wherein the quantity of said first transistors is greater than the quantity of said second transistors.

11. The circuit of claim 9, wherein each of said first transistors has a first drain, a first source, and a first gate, and each of said second transistors has a second drain, a second source, and a second gate, and said common first port couples together first drains and second drains, said common second port couples together first sources and second sources, and said common control port couples together first gates and second gates of said first transistors and said second transistors, respectively.

12. The circuit of claim 9, wherein all of said first transistors are substantially the same size, and all of said second transistors are the same size.

13. The circuit of claim 12, wherein all of said first transistors are substantially the same size as all of said second transistors.

14. The circuit of claim 9, wherein at least some of said first transistors vary in size and at least some of said second transistors vary in size.

15. The circuit of claim 9, wherein the quantity of said first transistors is less than the quantity of said second transistors.