Circuit for multiplication in a Galois field

• US 6,581,084 B1
• Filed: 01/14/2000
• Issued: 06/17/2003
• Est. Priority Date: 01/15/1999
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Romain, Fabrice, Monier, Guy, Lepareux, Marie-Noëlle
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US09/483,343
• Time in Patent Office: 1,250 Days
• Field of Search: 708/492
• US Class Current: 708/492
• CPC Class Codes: G06F 7/5275 using carry save adders
• CPC Class Codes: G06F 7/724 Finite field arithmetic for error detection or correction in general H03M13/00, in computers G06F11/10

Abstract

A multiplication circuit with an accumulator is provided. The multiplication circuit includes first latch circuits, second latch circuits, and elementary adders that are cascade-coupled to one another in series through the first latch circuits. Each of the adders has its carry output coupled to one of its inputs through one of the second latch circuits. Additionally, cancellation circuitry cancels the contents of each of the second latch circuits at least during selected multiplication operations so as to carry out multiplication operations in a Galois field. In some preferred embodiments, the cancellation circuitry includes a logic gate that receives a selection signal indicating the mode of operation, and the logic gate sets and holds the second latch circuits at zero when the selection signal indicates that the multiplication operation is to be done in a Galois field. In other preferred embodiments, the cancellation circuitry includes logic gates that are each associated with a pair formed by one of the adders and the associated second latch circuit. Also provided is a method for performing a multiplication operation in a Galois field using a multiplication circuit with an accumulator.

Claims

1. A multiplication circuit with an accumulator, said multiplication circuit comprising:

a plurality of first latch circuits;

a plurality of second latch circuits;

a plurality of elementary adders each having a result output and a carry output, the adders being cascade-coupled to one another in series through the first latch circuits, each of the adders having its carry output coupled to one of its inputs through one of the second latch circuits; and

cancellation circuitry for canceling the contents of each of the second latch circuits at least during selected multiplication operations so as to carry out multiplication operations in a Galois field.

2. The circuit as defined in claim 1, wherein the cancellation circuitry includes a logic gate that receives a selection signal indicating the mode of operation in which the multiplication circuit is to operate.

3. The circuit as defined in claim 2, wherein when the selection signal indicates that the multiplication operation is to be done in a Galois field, the logic gate sets and holds the second latch circuits at zero.

4. The circuit as defined in claim 1, wherein the cancellation circuitry includes a plurality of logic gates, each of the logic gates being associated with a pair formed by one of the adders and the associated second latch circuit.

5. The circuit as defined in claim 4, wherein each of the logic gates is coupled between the carry output of one of the adders and an input of the associated second latch circuit.

6. The circuit as defined in claim 5, wherein the logic gates are inverters and the outputs of the second latch circuits are inverter outputs.

7. The circuit as defined in claim 4, wherein the logic gates are inverters and the outputs of the second latch circuits are inverter outputs.

8. The circuit as defined in claim 1, wherein the adders are three-input adders.

9. A processor having a computation circuit with an accumulator, said computation circuit comprising:

a plurality of first latch circuits;

a plurality of second latch circuits;

a plurality of elementary adders each having a result output and a carry output, the adders being cascade-coupled to one another in series through the first latch circuits, each of the adders having its carry output coupled to one of its inputs through one of the second latch circuits; and

cancellation circuitry for canceling the contents of each of the second latch circuits at least during selected multiplication operations so as to carry out multiplication operations in a Galois field.

10. The processor as defined in claim 9, wherein the cancellation circuitry includes a logic gate that receives a selection signal indicating the mode of operation in which the computation circuit is to operate.

11. The processor as defined in claim 10, wherein when the selection signal indicates that the multiplication operation is to be done in a Galois field, the logic gate sets and holds the second latch circuits at zero.

12. The processor as defined in claim 9, wherein the cancellation circuitry includes a plurality of logic gates, each of the logic gates being associated with a pair formed by one of the adders and the associated second latch circuit.

13. The processor as defined in claim 12, wherein each of the logic gates is coupled between the carry output of one of the adders and an input of the associated second latch circuit.

14. The processor as defined in claim 12, wherein the logic gates are inverters and the outputs of the second latch circuits are inverter outputs.

15. A method for performing a multiplication operation in a Galois field using a multiplication circuit with an accumulator, the multiplication circuit including a plurality of elementary adders that are cascade-coupled to one another in series through a plurality of first latch circuits, said method comprising the steps of:

for each adder, coupling a carry output of the adder to one of the inputs of the adder through one of a plurality of second latch circuits; and

canceling the carry value stored in each of the second latch circuits when carrying out a multiplication operation in a Galois field.

16. The method as defined in claim 15, wherein in the canceling step, the stored carry values are canceled by setting and holding each of the second latch circuits at zero.

17. The method as defined in claim 16, wherein in the canceling step, each of the second latch circuits is set and held at zero at each cycle of a clock signal.

18. The method as defined in claim 15, wherein in the canceling step, each of the stored carry values is canceled through a logic gate that is coupled between the corresponding adder and the associated second latch circuit.