PCI bridge having latency inducing serial bus

• US 6,581,125 B1
• Filed: 05/14/1999
• Issued: 06/17/2003
• Est. Priority Date: 05/14/1999
• Status: Expired due to Term

• Current Assignee: Future Link Systems, LLC (Vector Capital Corporation)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Lange, Ronald E., Evoy, David Ross
• Primary Examiner(s): Lefkowitz, Sumati
• Assistant Examiner(s): CHUNG TRANS, XUONG MY
• Application Number:
  US09/312,206
• Time in Patent Office: 1,495 Days
• Field of Search: 710/305, 710/306, 710/310, 710/311, 710/312, 710/313, 710/314, 710/315, 710/300, 710/301, 710/302, 710/303, 710/304
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

A computer system includes a host processor, a first PCI bus, a second PCI bus and a bus bridge. The first PCI bus is coupled with the host processor. The bus bridge interconnects the first and second PCI buses. The bus bridge includes a first portion having a first bridge memory, a second portion having a second bridge memory, and a latency inducing serial bus interconnecting the first portion and the second portion. A method is also taught.

Claims

1. A computer system comprising:

a host processor;

a first PCI bus coupled with the host processor;

a second PCI bus;

a bus bridge interconnecting the first and second PCI buses, the bus bridge including;

a first portion having a first bridge memory;

a second portion having a second bridge memory; and

a latency inducing serial bus adapted to continuously provide FIFO status bits from the first portion to the second portion.

2. The computer system of claim 1 wherein the first bridge memory and the second bridge memory each comprise a transmitting FIFO queue and a receiving FIFO queue.

3. The computer system of claim 1 wherein the first portion includes a first FIFO queue and the second portion includes a second FIFO queue.

4. The computer system of claim 1 further comprising a connector interposed between the first portion and the second portion, and operative to removably couple the first portion with the second portion.

5. The computer system of claim 1 wherein the first portion comprises a primary side of the bridge, the primary side of the bridge including a first configuration register having read/write registers.

6. The computer system of claim 1 wherein the first portion comprises a primary side of the bridge, the second portion comprises a secondary side of the bridge, and the secondary side comprises a second configuration register including read/write registers.

7. The computer system of claim 1 wherein the first bridge memory includes a transmitting FIFO queue and a receiving FIFO queue, and the second bridge memory includes a transmitting FIFO queue and a receiving FIFO queue.

8. The computer system of claim 1 wherein the serial bus comprises a serial communication link configured to transmit idle packets and data packets between the first bridge memory and the second bridge memory.

9. A bridge coupled between a first bus and a second bus, comprising:

a first bridge portion having a first bridge memory and a first configuration register;

a second bridge portion having a second bridge memory and a second configuration register; and

a serial bus continuously coupling together the first bridge portion and the second bridge portion so as to provide FIFO status bits from the first bridge portion to the second bridge portion.

10. The bridge of claim 9 wherein the first bridge memory comprises a first FIFO queue and the second bridge memory comprises a second FIFO queue.

11. The bridge of claim 10 wherein the first FIFO queue and the second FIFO queue each comprise a transmitting FIFO queue and a receiving FIFO queue.

12. The bridge of claim 9 wherein the serial bus comprises a latency inducing serial communication link.

13. The bridge of claim 12 wherein the serial communication link is configured to transmit idle packets and data packets between the first bridge memory and the second bridge memory.

14. A method of mating a first PCI bus with a second PCI bus, the first PCI bus provided by a first agent and the second PCI bus provided by a second agent, the method comprising the steps of:

providing a bus bridge having a first portion with a first bridge memory and a second portion with a second bridge memory, wherein the first portion and the second portion are continuously connected for communication of data and FIFO status bits by a serial bus;

transmitting data between the first portion and the second portion; and

when a receiving portion of one of the first bridge memory and the second bridge memory approaches an overflow limit, transmitting a threshold signal to a transmitting portion of the other of the first bridge memory and the second bridge memory to prevent overflow of the receiving portion.

15. The method of claim 14 wherein the step of transmitting a threshold signal comprises transferring FIFO status bits from one of the first bridge memory and the second bridge memory to the other of the first bridge memory and the second bridge memory, and monitoring receipt of the transmitted FIFO status bits to prevent overrunning memory space in the other of the first bridge memory and the second bridge memory.

16. The method of claim 14 wherein a the first portion and the second portion are run on separate unsynchronized clocks, and wherein the step of transmitting a threshold signal comprises allocating a number of available memory locations required to continue receiving information that is set by:

a) the amount of latency required to get a threshold signal from a receiving FIFO queue in one of the first and second bridge memories to a transmitting FIFO queue in the other of the first and second bridge memories; and

to stop the transmission of new information packets; and

b) the number of packets still within a transmission path of the serial bus.

17. The method of claim 16 wherein the first bridge memory and the second bridge memory each comprise a transmitting FIFO queue and a receiving FIFO queue.