Method for controlling a semiconductor manufacturing process

• US 6,582,973 B1
• Filed: 04/05/2002
• Issued: 06/24/2003
• Est. Priority Date: 04/05/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Krishnagiri, Padmanabh, Laaksonen, Reima Tapani
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LUK, OLIVIA T
• Application Number:
  US10/117,726
• Time in Patent Office: 445 Days
• Field of Search: 438/4, 438/5, 438/6, 438/14, 438/15, 438/16, 438/17
• US Class Current: 438/5
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A method for dynamically controlling a semiconductor manufacturing process for producing a semiconductor component includes performing a plurality of process segments. Each respective process segment is performed for a respective processing interval. The method includes the steps of: (a) determining a relationship among respective process intervals for at least two particular process segments of the plurality of process segments; (b) determining a first respective process interval required for a first particular process segment to effect a desired result in the semiconductor component; and (c) using the relationship to establish the respective process interval required for at least one selected particular process segment in order to fix the respective process interval for a controlled process segment other than the at least one selected particular process segment.

Claims

1. A method for dynamically controlling a semiconductor manufacturing process;

said process producing a semiconductor component by performing a plurality of process segments;

each respective process segment of said plurality of process segments being performed for a respective processing interval;

the method comprising the steps of;

(a) determining a relationship among respective process intervals for at least two particular process segments of said plurality of process segments;

(b) determining a first said respective process interval required for a first said particular process segment to effect a desired result in said semiconductor component; and

(c) using said relationship to establish said respective process interval required for at least one selected said particular process segment in order to fix said respective process interval for a controlled process segment;

said controlled process segment being another said particular process segment than said at least one selected particular process segment.

2. A method for dynamically controlling a semiconductor manufacturing process as recited in claim 1 wherein said desired result is establishment of a predetermined critical dimension in said semiconductor component.

3. A method for dynamically controlling a semiconductor manufacturing process as recited in claim 1 wherein said relationship is expressed in terms relating said respective process interval for said controlled process segment as a function of respective process intervals for said at least two particular process segments other than said controlled process segment.

4. A method for dynamically controlling a semiconductor manufacturing process as recited in claim 2 wherein said relationship is expressed in terms relating said respective process interval for said controlled process segment as a function of respective process intervals for said at least two particular process segments other than said controlled process segment.

5. A method for dynamically controlling manufacture of a semiconductor device;

said manufacture including a plurality of etch process steps;

each respective etch step of said plurality of etch steps being performed for a respective etch interval;

the method comprising the steps of;

(a) ascertaining a relationship among three specific etch intervals of said plurality of etch intervals;

(b) determine a first said respective etch interval required for a first said specific etch interval to effect a predetermined result in said semiconductor device;

(c) using said relationship to determine said respective etch interval for a second said specific etch interval of said three specific etch intervals in order to fix a third said specific etch interval of said three specific etch intervals.

6. A method for dynamically controlling manufacture of a semiconductor device as recited in claim 5 wherein said predetermined result is establishment of a critical dimension in said semiconductor component.

7. A method for dynamically controlling manufacture of a semiconductor device as recited in claim 5 wherein said relationship is expressed in terms relating said third specific etch interval as a function of said first specific etch interval and said second specific etch interval.

8. A method for dynamically controlling manufacture of a semiconductor device as recited in claim 7 wherein said relationship is expressed in terms relating said third specific etch interval as a function of said first specific etch interval and said second specific etch interval.

9. An apparatus for effecting a plurality of communication connections between at least two switching devices in a communication system as recited in claim 8 wherein at least one of said first router interface device and said second router interface device comprises a plurality of router selection devices;

each respective router selection device of said plurality of router selection devices affecting at least one respective selected communication connection of said plurality of communication connections.

10. A method for dynamically controlling a process for manufacturing a semiconductor device;

said process including a plurality of process segments;

each respective process segment of said plurality of process segments being performed for a respective processing interval;

the method comprising the steps of;

(a) determining a relationship among three specific processing intervals for three specific process segments of said plurality of process segments;

(b) performing a first said specific process segment for a first processing interval;

said first processing interval being established when a predetermined result is achieved in said semiconductor device;

(c) using said relationship to determine a second processing interval for a second said specific process segment of said three specific process segments;

said second processing interval being established appropriately to fix a third processing interval for said third specific processing segment; and

(d) performing said second specific process segment for said second processing interval.

11. A method for dynamically controlling a process for manufacturing a semiconductor device as recited in claim 10 wherein said predetermined result is establishment of a critical dimension in said semiconductor device.

12. A method for dynamically controlling a process for manufacturing a semiconductor device as recited in claim 10 wherein said relationship is expressed in terms relating said third processing interval as a function of said first processing interval and said second processing interval.

13. A method for dynamically controlling a process for manufacturing a semiconductor device as recited in claim 11 wherein said relationship is expressed in terms relating said third processing interval as a function of said first processing interval and said second processing interval.