Thyristor-based device having extended capacitive coupling
First Claim
1. A semiconductor device comprising:
- a thyristor having contiguous regions including at least two contiguous regions of different polarity, a first one of the contiguous regions having a portion in a current path traversing two regions of the thyristor other than the first one of the contiguous regions and having an extended portion arranged outside the current path; and
a conductive structure facing and capacitively coupled to the extended portion of the first one of the contiguous regions, the conductive structure being adapted to control current passing through the thyristor via the capacitive coupling.
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Abstract
A thyristor-based semiconductor device has a thyristor that exhibits increased capacitive coupling between a conductive structure and a portion of a thyristor. According to an example embodiment of the present invention, the thyristor-based semiconductor device is manufactured having an extended portion that is outside a current path through the thyristor and that capacitively couples a conductive structure to a portion of the thyristor for controlling the current through the path. In one particular implementation, the extended portion extends from a base region of the thyristor and is outside of a current path through the base region and between an adjacent base region and an adjacent emitter region. A gate is formed capacitively coupled to the base region via the extended portion. In this manner, the control of the thyristor with the gate exhibits increased capacitive coupling, as compared to the control without the extended portion.
53 Citations
23 Claims
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1. A semiconductor device comprising:
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a thyristor having contiguous regions including at least two contiguous regions of different polarity, a first one of the contiguous regions having a portion in a current path traversing two regions of the thyristor other than the first one of the contiguous regions and having an extended portion arranged outside the current path; and
a conductive structure facing and capacitively coupled to the extended portion of the first one of the contiguous regions, the conductive structure being adapted to control current passing through the thyristor via the capacitive coupling. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
a first emitter region extending below the buried insulator layer;
a first base region extending into the opening in the insulator layer and contiguously adjacent the first emitter region;
a second base region extending laterally on the insulator layer and contiguously adjacent the first base region, a portion of the second base region including the extended portion;
a second emitter region contiguously adjacent the second base region and including a source/drain region of the pass gate; and
wherein the conductive structure is formed over the second base region and extending laterally over the extended portion.
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18. The semiconductor device of claim 1, further comprising a plurality of word lines having a dielectric formed thereon, at least one of the word lines including a gate of a pass gate that is coupled to the thyristor, wherein the thyristor extends over at least two of the word lines.
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19. The semiconductor device of claim 1, wherein the conductive structure is adapted to capacitively couple a signal to control the current passing through the thyristor independently from any MOS inversion channel formation against the first contiguous region.
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20. A memory array having a plurality of memory cells wherein at least one of the memory cells comprises:
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a thyristor having contiguous regions including at least two contiguous regions of different polarity, a first one of the contiguous regions having a portion in a current path traversing two regions of the thyristor other than the first one of the contiguous regions and having an extended portion arranged outside the current path; and
a conductive structure facing and capacitively coupled to the extended portion of the first one of the contiguous regions, the conductive structure being adapted to control current passing through the thyristor via the capacitive coupling.
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21. A memory cell comprising:
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a thin capacitively-coupled thyristor body having an anode end portion including an N-doped base region and a P+ doped emitter region, and having a cathode end portion including a P-doped base region and an N+ doped emitter region, a first one of the base regions having a portion in a current path extending between the other base region and the emitter at the thyristor end portion that includes the first one of the base regions and having an extended portion outside the current path and extended from the thyristor body;
a gate dielectric on the extended portion of the first one of the base regions;
a control gate on the gate dielectric, capacitively coupled to the extended portion via the gate dielectric and adapted to control the thyristor via the capacitive coupling; and
a pass gate transistor having a gate and two source/drain regions, one of the source/drain regions being electrically coupled to one of the emitter regions.- View Dependent Claims (22)
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23. A memory array having a plurality of memory cells, at least one of the memory cells comprising:
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a thin capacitively-coupled thyristor body having an anode end portion including an N-doped base region and a P+ doped emitter region, and having a cathode end portion including a P-doped base region and an N+ doped emitter region, a first one of the base regions having a portion in a current path extending between the other base region and the emitter at the thyristor end portion that includes the first one of the base regions and having an extended portion outside the current path and extended from the thyristor body;
a gate dielectric on the extended portion of the first one of the base regions;
a control gate on the gate dielectric, capacitively coupled to the extended portion via the gate dielectric and adapted to control the thyristor via the capacitive coupling; and
a pass gate transistor having a gate and two source/drain regions, one of the source/drain regions being electrically coupled to one of the emitter regions.
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Specification