Reduced cost, high speed circuit test arrangement
First Claim
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1. A system comprising:
- a control computer arranged to produce test algorithm information;
a plurality of integrated circuits for executing the test algorithm information to generate test signals;
a serial loop for serially communicating data packets from the control computer to the plurality of integrated circuits, wherein the data packets each include an address portion corresponding to at least one of the integrated circuits and a data portion including the test algorithm information; and
a plurality of sockets, each coupled to a respective one of the plurality of integrated circuits, and each for receiving a respective circuit to be operated so that test signals generated by the corresponding integrated circuit according to the test algorithm information are communicated to the received circuit.
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Abstract
An integrated circuit device test arrangement includes a plurality of microcomputers. Each of the microcomputers is interconnected directly through a separate test socket to a separate integrated circuit device that is inserted into the test socket. A device tester is coupled to the plurality of microcomputers for transmitting information between the device tester and the plurality of microcomputers. Each microcomputer contains instructions and data for performing a test routine on the associated integrated circuit device and transmitting selected results of the test routine to the tester.
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Citations
18 Claims
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1. A system comprising:
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a control computer arranged to produce test algorithm information;
a plurality of integrated circuits for executing the test algorithm information to generate test signals;
a serial loop for serially communicating data packets from the control computer to the plurality of integrated circuits, wherein the data packets each include an address portion corresponding to at least one of the integrated circuits and a data portion including the test algorithm information; and
a plurality of sockets, each coupled to a respective one of the plurality of integrated circuits, and each for receiving a respective circuit to be operated so that test signals generated by the corresponding integrated circuit according to the test algorithm information are communicated to the received circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A system comprising:
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a control computer for generating test algorithm information including instructions and data;
a plurality of microprocessors, each capable of executing test algorithm information received from the control computer;
a serial bus, serially coupling the control computer and the plurality of microprocessors, for communicating data packets from the control computer to the plurality of microprocessors, wherein the data packets each include an address portion corresponding to at least one of the microprocessors and a data portion including the test algorithm information; and
a plurality of sockets, each for receiving a circuit to be tested, and each coupled to a corresponding one of the plurality of microprocessors, for communicating test signals generated by the corresponding microprocessor according to the test algorithm information, to the circuit to be tested. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification