Active matrix type liquid crystal display device, and substrate for the same

• US 6,583,777 B2
• Filed: 05/04/2001
• Issued: 06/24/2003
• Est. Priority Date: 05/07/1998
• Status: Expired due to Term

• Current Assignee: Eidos Advanced Display LLC
• Original Assignee: ALPS Electric Company Limited (Alps Alpine Co., Ltd.), LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Hebiguchi, Hiroyuki, Kawahata, Ken
• Primary Examiner(s): Hjerpe, Richard
• Assistant Examiner(s): Nguyen, Kevin M.
• Application Number:
  US09/849,904
• Publication Number:
  US 20010015715A1
• Time in Patent Office: 781 Days
• Field of Search: 345/92, 345/87, 345/100, 345/103, 349/139, 349/42
• US Class Current: 345/92
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0876 Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

An active matrix type liquid crystal display device has a plurality of data lines and a plurality of gate lines formed on a substrate in matrix fashion, TFTs and pixel electrodes being provided at both sides of the data lines so as to correspond with each of the plurality of gate lines, and the plurality of gate lines are positioned such that the pixel electrodes at both sides of the data lines are controlled by signals from one of the two gate lines sandwiching the pixel electrodes, i.e., either the first or second gate line. Also, the gate electrodes comprising TFTs are comprised of gate lines themselves, so that the drain electrodes electrically connected to the pixel electrodes traverse the gate electrodes. Thus, the pixels can be driven with fewer data lines than with known arrangements.

Claims

1. An active matrix type liquid crystal display device substrate, comprising:

a plurality of data lines and a plurality of gate lines provided on a substrate in a matrix form, the data lines being without overlap; and

thin-film transistors and pixel electrodes connecting to said thin-film transistors provided on one side of each of said data lines, corresponding with each of said plurality of gate lines, adjacent gate lines having one of the thin-film transistors and pixel electrodes disposed therebetween;

wherein drain electrodes of said thin-film transistors connected with said pixel electrodes are provided on the same side of the gate lines as gate electrodes extending from said gate lines, with at least two of said data lines being electrically connected; and

wherein thin-film transistors connected to each of said connected data lines are each controlled by a different ate line of the plurality of gate lines.

2. An active matrix type liquid crystal display device substrate according to claim 1, wherein said at least two electrically connected data lines are mutually and directly connected at both sides of said data lines, at least.

3. An active matrix type liquid crystal display device substrate according to claim 1, wherein said data lines are electrically connected at intervals of odd numbers.

4. An active matrix type liquid crystal display device substrate according to claim 1, wherein at least one of the gate lines whose gate electrode is unconnected to one of said pixel electrodes traverses said pixel electrodes underneath said pixel electrodes to form a storing capacity in cooperation with the one of the pixel electrodes.

5. An active matrix type liquid crystal display device, comprising a pair of opposedly positioned substrates whereby liquid crystal is held therebetween, wherein one of said substrates is a substrate according to claim 1.

6. An active matrix type liquid crystal display device substrate according to claim 1, wherein adjacent pairs of data lines are electrically connected.

7. An active matrix type liquid crystal display device substrate according to claim 6, wherein no data line of one pair of data lines electrically connected overlaps with any other data line of another pair of data lines electrically connected.

8. An active matrix type liquid crystal display device substrate according to claim 7, wherein at least one of the gate lines whose gate electrode is unconnected to one of the pixel electrodes traverses the pixel electrodes underneath the pixel electrodes to form a storing capacity in cooperation with the one of the pixel electrodes.

9. An active matrix type liquid crystal display device substrate according to claim 1, wherein sets of three adjacent data lines are electrically connected.

10. An active matrix type liquid crystal display device substrate according to claim 9, wherein no data line of one set of three data lines electrically connected overlaps with any other data line of another set of three data lines electrically connected.

11. An active matrix type liquid crystal display device substrate according to claim 10, wherein each set of three data lines has sets of three thin-film transistors and pixel electrodes associated with the set of three data lines, each thin-film transistor and pixel electrode in one set of three thin-film transistors and pixel electrodes connected with a unique gate line, the set of gate lines connected with each set of three thin-film transistors and pixel electrodes being arranged consecutively.

12. An active matrix type liquid crystal display device substrate according to claim 11, wherein no two thin-film transistors and pixel electrodes connected with adjacent gate lines are connected with the same data line.

13. An active matrix type liquid crystal display device substrate according to claim 12, wherein the thin-film transistors and pixel electrodes in each set of three thin-film transistors and pixel electrodes are arranged such that adjacent thin-film transistors and pixel electrodes are connected with adjacent gate lines and adjacent data lines.

17. An active matrix type liquid crystal display device substrate according to claim 1, wherein the adjacent thin-film transistors connected with the same data line have more than one gate line disposed therebetween.

18. An active matrix type liquid crystal display device substrate according to claim 1, wherein adjacent pixel electrodes connected with transistors that are connected with the same data line have more than one gate line disposed thereunder to form a storing capacity in cooperation with the more than one gate line.

14. An active matrix type liquid crystal display device substrate, comprising:

a plurality of data lines and a plurality of gate lines provided on a substrate in a matrix, the data lines being without overlap; and

thin-film transistors and pixel electrodes connected with the thin-film transistors provided on one side of each of the data lines, corresponding with each of the plurality of gate lines, adjacent thin-film transistors connected to the same data line having multiple gate lines therebetween, each of the multiple gate lines disposed adjacent to each other;

wherein drain electrodes of the thin-film transistors connected with the pixel electrodes are provided on the same side of the gate lines as gate electrodes extending from the gate lines, with a plurality of adjacent data lines being electrically connected, the thin-film transistors connected to each of the plurality of adjacent data lines are each controlled by a different gate line of the plurality of gate lines.

15. An active matrix type liquid crystal display device, comprising a pair of opposedly positioned substrates whereby liquid crystal is held therebetween, wherein one of said substrates is a substrate according to claim 14.

16. An active matrix type liquid crystal display device substrate according to claim 14, wherein the electrically connected data lines are mutually connected at both sides of the electrically connected data lines.