Electrically alterable non-volatile memory with N-bits per cell

• US 6,584,012 B2
• Filed: 06/04/2002
• Issued: 06/24/2003
• Est. Priority Date: 02/08/1991
• Status: Expired due to Fees

• Current Assignee: BTG International Inc. (Boston Scientific Corporation)
• Original Assignee: BTG International Inc. (Boston Scientific Corporation)
• Inventors: Banks, Gerald J.
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US10/160,402
• Publication Number:
  US 20020186587A1
• Time in Patent Office: 385 Days
• Field of Search: 365/185.03, 365/185.22, 365/185.33
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell is conducted by applying a plurality of programming signals having different characteristics to the cell. The programming signals include at least a first programming signal which programs the cell by a first increment and a subsequent programming signal which programs the cell by a second increment smaller than the first increment. As the cell is being programmed to a selected state, its programming status is verified independently of reference values bounding the memory states. For this purpose, a signal indicative of the programming status (e.g., the cell'"'"'s bit line signal) is compared with a reference signal corresponding to the selected state but having a value different from the reference value or values bounding the selected state. The programming operation can thus be controlled without actually reading the memory state of the cell.

Claims

1. For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a memory FET having a storage structure, electrons being capable of being injected into the storage structure from a drain-source current path in each of the plurality of non-volatile multi-level memory cells, a method of operating the electrically alterable non-volatile multi-level semiconductor memory device, comprising:

setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells selectively among a plurality of states including at least a first state, a second state, a third state and a fourth state in accordance with information to be stored in the one non-volatile multi-level memory cell;

generating programming reference values for programming the first, second and third states, and generating read reference values, which are different from the programming reference values, for reading the first, second and third states;

verifying programming of the one non-volatile multi-level memory cell among the first, second and third states by comparing the parameter of the one non-volatile multi-level memory cell with the programming reference values, each operation of setting the parameter to a selected one of the first, second and third states being conducted until it is verified that the parameter of the one non-volatile multi-level memory cell has been set to the selected state; and

reading the one non-volatile multi-level memory cell using the read reference values to evaluate the parameter of the one non-volatile multi-level memory cell,

wherein the read reference values are values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits,

wherein the normal read operation includes evaluating the parameter of the one non-volatile multi-level memory cell with a sense circuit using the read reference values, and

wherein the plurality of non-volatile multi-level memory cells are arranged in a matrix of rows and columns disposed substantially in a rectangle that has a first side, a second side, a third side and a fourth side, the first side and the second side intersect with each other substantially perpendicularly, a plurality of word lines coupled with gate electrodes of memory FET'"'"'s of the multi-level memory cells and the first side of the rectangle intersect with each other substantially perpendicularly, a plurality of bit lines coupled with drain-source current paths of memory FET'"'"'s of the multi-level memory cells and the second side of the rectangle intersect with each other substantially perpendicularly, a row select circuit is disposed at the first side of the rectangle for coupling with the plurality of word lines, and peripheral circuitry, including a column select circuit and the sense circuit, is disposed at the second side of the rectangle.

2. The method of operating the electrically alterable non-volatile multi-level memory according to claim 1,

wherein an operation of setting the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

3. The method of operating the electrically alterable non-volatile multi-level memory according to claim 2,

wherein an operation of setting the parameter includes a program operation in which electrons are injected into the storage structure of the one non-volatile multi-level memory cell.

4. The method of operating the electrically alterable non-volatile multi-level memory according to claim 1,

wherein electrons are capable of being injected into the storage structure from the drain-source current path in each of the plurality of non-volatile multi-level memory cells by hot electron injection.

5. The method of operating the electrically alterable non-volatile multi-level memory according to claim 1,

wherein electrons are capable of being injected into the storage structure from the drain-source current path in each of the plurality of non-volatile multi-level memory cells by Fowler-Nordheim tunnelling.

6. The method of operating the electrically alterable non-volatile multi-level memory according to claim 1,

wherein the drain-source current paths of memory FET'"'"'s of a group of the plurality of non-volatile multi-level memory cells are coupled with a bit line in parallel.

7. An electrically alterable non-volatile multi-level memory device, comprising:

a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a memory FET having a storage structure, electrons being capable of being injected into the storage structure from a drain-source current path in each of the plurality of non-volatile multi-level memory cells, and

wherein operations of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells selectively among a plurality of states including at least a first state, a second state, a third state and a fourth state are carried out in accordance with information to be stored in the one non-volatile multi-level memory cell,

wherein programming reference values for programming the first, second and third states are generated, and read reference values, which are different from the programming reference values, for reading the first, second and third states are generated,

wherein operations of verifying programming of the one non-volatile multi-level memory cell among the first, second and third states are carried out and include comparing the parameter of the one non-volatile multi-level memory cell with the programming reference values, each operation of setting the parameter to a selected one of the first, second and third states being conducted until it is verified that the parameter of the one non-volatile multi-level memory cell has been set to the selected state,

wherein operations of reading the one non-volatile multi-level memory cell are carried out using the read reference values to evaluate the parameter of the non-volatile multi-level memory cell,

wherein the read reference values are values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits,

wherein the normal read operation includes evaluating the parameter of the one non-volatile multi-level memory cell with a sense circuit using the read reference values, and

wherein the plurality of non-volatile multi-level memory cells are arranged in a matrix of rows and columns disposed in substantially a rectangle that has a first side, a second side, a third side and a fourth side, the first side and the second side intersect with each other substantially perpendicularly, a plurality of word lines coupled with gate electrodes of memory FET'"'"'s of the multi-level memory cells and the first side of the rectangle intersect with each other substantially perpendicularly, a plurality of bit lines coupled with drain-source current paths of memory FET'"'"'s of the multi-level memory cells and the second side of the rectangle intersect with each other substantially perpendicularly, a row select circuit is disposed at the first side of the rectangle for coupling with the plurality of word lines, and peripheral circuitry, including a column select circuit and the sense circuit, is disposed at the second side of the rectangle.

8. The electrically alterable non-volatile multi-level memory device according to claim 7,

wherein an operation of setting the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

9. The electrically alterable non-volatile multi-level memory device according to claim 8,

wherein an operation of setting the parameter includes a program operation in which electrons are injected into the storage structure of the one non-volatile multi-level memory cell.

10. The electrically alterable non-volatile multi-level memory device according to claim 9,

wherein each of the plurality of bit lines transfers information indicating data stored in a memory cell, wherein drain regions of said multi-level memory cells of said group in said matrix are coupled to a first bit line of said plurality of bit lines, drain regions of multi-level memory cells of a second group adjacent to said group in said matrix are coupled to a second bit line adjacent to said first bit line in said plurality of bit lines, and drain regions of multi-level memory cells of a third group adjacent to said second group in said matrix are coupled to a third bit line adjacent to said second bit line in said plurality of bit lines.

11. The electrically alterable non-volatile multi-level memory device according to claim 7,

wherein electrons are capable of being injected into the storage structure from the drain-source current path in each of the plurality of non-volatile multi-level memory cells by hot electron injection.

12. The electrically alterable non-volatile multi-level memory device according to claim 7,

wherein electrons are capable of being injected into the storage structure from the drain-source current path in each of the plurality of non-volatile multi-level memory cells by Fowler-Nordheim tunnelling.

13. The electrically alterable non-volatile multi-level memory device according to claim 7,

wherein the drain-source current paths of memory FET'"'"'s of a group of the plurality of non-volatile multi-level memory cells are coupled with a bit line in parallel.