Semiconductor integrated circuit device

• US 6,584,033 B2
• Filed: 04/24/2002
• Issued: 06/24/2003
• Est. Priority Date: 08/16/1999
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Ayukawa, Kazushige, Watanabe, Takao, Narita, Susumu
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US10/128,254
• Publication Number:
  US 20020118591A1
• Time in Patent Office: 426 Days
• Field of Search: 365/230.03, 365/196, 365/189.01, 365/239, 365/189.04, 365/230.01, 365/230.09
• US Class Current: 365/230.03
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory macro is a combination of functional modules such as a main amplifier module, memory bank modules of which each memory bank operates independently, a power source circuit, etc. The storage capacity of the memory macro can be easily changed from a large capacity to a small one by changing the number of the memory bank modules. A control circuit in the memory bank modules of the memory macro has an additional address comparing function. Therefore, the same page can be accessed at high speed without providing any control circuit outside the memory macro. In addition, a module having a function such as a memory access sequence control is provided and, when memory access is made, identification information is issued at the time of inputting/outputting address or data. Therefore, high-speed memory access can be realized by checking the coincidence between the data and address with the ID and controlling the memory access sequence so that the address inputting order and data outputting order can be changed.

Claims

1. A semiconductor device comprising:

a plurality of memory banks having a plurality of memory cells, bit lines and word lines;

a plurality of sense amplifiers coupled to said plurality of memory cells; and

a memory controller for controlling and issuing commands to said plurality of memory banks in response to commands from a CPU;

wherein the sequence of the data read out from the memory bank is different from the sequence of the corresponding address received from said CPU by said memory controller.

2. The semiconductor device according to claim 1, wherein said memory cells are DRAM cells.

3. The semiconductor device according to claim 1, further comprising:

a global bit line extending in a first direction crossing said plurality of memory banks;

wherein each memory bank has a plurality of bit lines extending in said first direction.

4. The semiconductor device according to claim 1, wherein said sequence of the data read out from the memory bank is set in an order that data read out from the same word line are continuous.

5. The semiconductor device according to claim 1, further comprising:

a circuit to form a correspondence between the received address and data read out from the memory bank.