Methods and apparatus for increasing scanning modes

• US 6,584,167 B1
• Filed: 04/26/2002
• Issued: 06/24/2003
• Est. Priority Date: 04/26/2002
• Status: Expired due to Fees

• Current Assignee: GE Medical Systems Global Technology Company LLC (GE Healthcare Technologies, Inc.)
• Original Assignee: GE Medical Systems Global Technology Company LLC (GE Healthcare Technologies, Inc.)
• Inventors: Ikhlef, Abdelaziz, Zeman, Gregory
• Primary Examiner(s): BRUCE, DAVID VERNON
• Application Number:
  US10/133,897
• Time in Patent Office: 424 Days
• Field of Search: 378/4, 378/8, 378/15, 378/19, 378/901
• US Class Current: 378/19
• CPC Class Codes: A61B 6/032 Transmission computed tomography [CT]
• CPC Class Codes: A61B 6/4085 Cone-beams
• CPC Class Codes: A61B 6/5205 involving processing of raw data to produce diagnostic data
• CPC Class Codes: A61B 6/56 Details of data transmission or power supply, e.g. use of slip rings
• CPC Class Codes: Y10S 378/901 Computer tomography program or processor

Abstract

A method for transmitting a scan mode to an imaging system includes loading a least significant nibble into a first latch register and loading a most significant nibble into a second latch register such that a byte of information is received at a decoder.

Claims

1. A method for transmitting a scan mode to an imaging system, said method comprising:

loading a least significant nibble into a first latch register; and

loading a most significant nibble into a second latch register such that a byte of information is received at a decoder.

2. A method in accordance with claim 1 further comprising:

transmitting a chip enable signal to the first latch register and the second latch register; and

transmitting a chip select signal to the first latch register and the second latch register.

3. A method in accordance with claim 2 wherein said transmitting a chip enable signal to the first latch register and the second latch register further comprises transmitting a chip enable signal to the first latch register and the second latch register approximately two microseconds after transmitting a chip select signal to the first latch register and the second latch register.

4. A method in accordance with claim 1 wherein said loading a least significant nibble into a first latch register comprises loading a least significant nibble into a first latch register configured to transmit data to a decoder when a chip select line is set to low and a chip enable line is set to high.

5. A method in accordance with claim 1 wherein said loading a most significant nibble into a second latch register comprises loading a most significant nibble into a second latch register configured to transmit data to a decoder when a chip select line is set to high and a chip enable line is set to high.

6. A method for transmitting a scan mode to an imaging system, said method comprising:

loading a least significant nibble into a first latch register including a D-Flip-Flop latch register configured to transmit data to a decoder when a chip select line is set to low and a chip enable line is set to high;

loading a most significant nibble into a second latch register configured to transmit data to a decoder when a chip select line is set to high and a chip enable line is set to high.

7. A method for transmitting a scan mode to an imaging system, said method comprising:

connecting an electrical cable including n data lines to a decoder; and

multiplexing the n data lines such that the decoder is operable in 2²ⁿ modes.

8. A method in accordance with claim 7 wherein said multiplexing the n data lines comprises:

loading a least significant nibble into a first latch register; and

loading a most significant nibble into a second latch register such that a byte of information is received at the decoder.

9. A method in accordance with claim 8 wherein said loading a least significant nibble into a first latch register comprises loading a least significant nibble into a first latch register when a chip select signal is set to low and a chip enable signal is set to high, and said loading a most significant nibble into a second latch register comprises loading a most significant nibble into a second latch register when the chip select signal is set to high and the chip enable signal is set to high.

10. A method in accordance with claim 9 wherein said loading a least significant nibble into a first latch register comprises loading a least significant nibble into a first latch register configured to transmit data to a decoder, and loading a most significant nibble into a second latch register comprises loading a most significant nibble into a second latch register configured to transmit data to the decoder.

11. A method in accordance with claim 9 wherein said loading a least significant nibble into a first latch register when a chip select signal is set to low and a chip enable signal is set to high, and said loading a most significant nibble into a second latch register when the chip select signal is set to high and the chip enable signal is set to high comprises transmitting the chip enable signal to the first latch register and the second latch register approximately two microseconds after transmitting the chip select signal to the first latch register and the second latch register.

12. A detector module for a computed tomographic imaging system assembly, said module comprising:

a scintillator array comprising a plurality of scintillation elements;

a photodiode array comprising a plurality of photodiodes optically coupled to said scintillator array;

a decoder coupled to said photodiode array, said decoder comprising a plurality of latch registers; and

a flexible cable electrically connected to said decoder assembly and configured to transmit signals representative of a light output by said scintillator array to said CT imaging system.

13. A detector in accordance with claim 12 wherein said electrical cable comprises exactly six decoder control lines electrically connected to said latch registers, wherein said six decoder control lines comprise two latch register control lines and four data lines.

14. A detector in accordance with claim 13 wherein said latch register control lines comprise a chip select line and a chip enable line.

15. A detector in accordance with claim 12 wherein said plurality of latch registers comprises a first latch register comprising a D-Flip-Flop latch register, a second latch register comprising a D-Flip-Flop latch register.

16. A computed tomographic (CT) imaging system, said imaging system comprising:

a detector array comprising a plurality of modules wherein each said module comprises;

a scintillator array comprising a plurality of scintillation elements;

a photodiode array comprising a plurality of photodiodes optically coupled to said scintillator array;

a decoder coupled to said photodiode array, said decoder comprising a plurality of latch registers; and

a flexible cable electrically connected to said decoder assembly, said cable comprising n data lines;

at least one radiation source; and

a computer coupled to said detector array and radiation source and configured to;

multiplex said n data lines such that said decoder is operable in 2²ⁿ modes.

17. A CT imaging system in accordance with claim 16 wherein to multiplex said n data lines such that said decoder is operable in 2²ⁿ modes, said computer further configured to transmit a chip enable signal to a first latch register and a second latch register approximately two microseconds after transmitting a chip select signal to said first latch register and said second latch register.

18. A CT imaging system in accordance with claim 16 wherein to multiplex said n data lines such that said decoder is operable in 2²ⁿ modes, said computer further configured to set a chip select line to low and set a chip enable line to high to load a least significant nibble into said first latch register.

19. A CT imaging system in accordance with claim 16 wherein to multiplex said n data lines such that said decoder is operable in 2²ⁿ modes, said computer further configured to set a chip select line to high and set a chip enable line to high to load a most significant nibble into said second latch register.

20. A CT imaging system in accordance with claim 17 wherein to transmit a chip enable signal to said first latch register and said second latch register, said computer further configured to transmit a chip enable signal to said first latch register and said second latch register approximately two microseconds after transmitting a chip select signal to said first latch register and said second latch register.

21. A computer readable medium encoded with a program executable by a computer for transmitting a scan mode to an imaging system, said program configured to instruct the computer to:

transmit a chip enable signal to a first latch register and a second latch register; and

transmit a chip select signal to said first latch register and said second latch register such that a byte of information is received at a decoder.

22. A computer readable medium in with claim 21 wherein to transmit a chip enable signal to said first latch register and said second latch register, said program further configured to transmit a chip enable signal to said first latch register and said second latch register approximately two microseconds after transmitting a chip select signal to said first latch register and said second latch register.

23. A computer readable medium in with claim 21 wherein to load a least significant nibble into said first latch register, said program further configured to set a chip select line to low and set a chip enable line to high to load a least significant nibble into said first latch register.

24. A computer readable medium in with claim 21 wherein to load a most significant nibble into said second latch register, said program further configured to set a chip select line to high and set a chip enable line to high to load a most significant nibble into said second latch register.