Method and apparatus enabling communication between an electric device and a battery

• US 6,584,329 B1
• Filed: 01/27/2000
• Issued: 06/24/2003
• Est. Priority Date: 01/27/1999
• Status: Expired due to Term

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Wendelrup, Heino, Kellerman, Michael, Rubbmark, Jan, Bengtsson, Jonas, Forsberg, Charles, Ptasinski, Kristoffer, Mercke, Johan
• Primary Examiner(s): VO, NGUYEN THANH
• Application Number:
  US09/492,341
• Time in Patent Office: 1,244 Days
• Field of Search: 455/572, 455/573, 455/88, 455/418-420, 455/67.1, 320/114, 320/136, 320/134
• US Class Current: 455/572
• CPC Class Codes: H02J 7/00036 Charger exchanging data with battery
• CPC Class Codes: H02J 7/00047 with provisions for charging different types of batteries

Abstract

Digital, serial communication over an interface between an electronic device (102) and a battery (103) attached thereto comprises transmission of bytes (300) consisting of a number of bits. Each bit is defined by one of a high level and a low level, and a leading bit (304) of each byte is of a first one of said high and low levels. The method comprises the step of transmitting the other of the high and low levels for a first period of time (403, 405) immediately prior to said leading bit (304). When the leading bit of a byte is always of the same level (i.e. either high or low) and a period of the opposite level precedes the leading bit, it is very easy and simple to ensure that the sending as well as the receiving party is ready for the communication to take place and adjusted to the actual direction of communication.

Claims

1. A method enabling digital, serial communication over an interface between an electronic device (102) and a battery (103) attached thereto, said digital, serial communication comprising transmission of bytes (300) consisting of a number of bits, each bit being defined by one of a high level and a low level, wherein a leading bit (304) of each byte is of a first one of said high and low levels,

characterized in that the method comprises the step of transmitting the other of said high and low levels for a first period of time (403, 405) immediately prior to said leading bit (304).

2. A method according to claim 1, characterized in that the method further comprises the steps of

transmitting each byte with a trailing bit (310) of the other of said high and low levels, and

transmitting the other of said high and low levels for a second period of time (405, 406) immediately following said trailing bit.

3. A method according to claim 2, characterized in that the sum of said first and second periods of time defines a waiting state between two consecutive bytes in the case where at least two bytes are transmitted following each other.

4. A method according to claim 3, characterized in that the direction of transmission is changed during said waiting state.

5. A method according to claim 4, characterized in that a byte transmitted in one direction over said interface is retransmitted in the opposite direction after the direction of transmission has been changed.

6. A method according to claim 2, characterized in that the interface is set to an idle state wherein the first one of said high and low levels is transmitted, if said second period of time (406) exceeds a preset value.

7. A method according to claim 6, characterized in that said first period of time (404) defines a wake-up state when a byte is transmitted as the first byte after an idle state.

8. An apparatus comprising

an electronic device (102),

a battery (103) attached thereto, and

means enabling digital, serial communication over an interface between the electronic device (102) and the battery (103), and comprising first communications circuitry (108) in the electronic device and second communications circuitry (117) in the battery,

said digital, serial communication comprising transmission between said first and second communications circuitry of bytes (300) consisting of a number of bits, each bit being defined by one of a high level and a low level, wherein a leading bit (304) of each byte is of a first one of said high and low levels,

characterized in that at least one of said first and second communications circuitry is adapted to transmit the other of said high and low levels for a first period of time (404, 405) immediately prior to said leading bit.

9. An apparatus according to claim 8, characterized in that the at least one of said first and second communications circuitry comprises

means for transmitting each byte with a trailing bit (310) of the other of said high and low levels, and means for transmitting the other of said high and low levels for a second period of time (405, 406) immediately following said trailing bit.

10. An apparatus according to claim 9, characterized in that the sum of said first and second periods of time constitutes a waiting state between two consecutive bytes in the case where at least two bytes are transmitted following each other.

11. An apparatus according to claim 10, characterized in that at least one of said first and second communications circuitry comprises means for changing the direction of transmission during said waiting state.

12. An apparatus according to claim 11, characterized in that at least one of said first and second communications circuitry comprises means for retransmitting a byte, transmitted in one direction over said interface, in the opposite direction after the direction of transmission has been changed.

13. An apparatus according to claim 9, characterized in that the interface is adapted to assume an idle state wherein the first one of said high and low levels is transmitted, if said second period of time (406) has exceeded a preset value.

14. An apparatus according to claim 13, characterized in that said second communications circuitry is adapted to assume a wake-up state defined by said first period of time (404) prior to receiving a byte as the first byte after an idle state.

15. An apparatus according to claim 8, characterized in that the electronic device is a cellular telephone.

16. A battery comprising means enabling digital, serial communication over an interface between the battery and an electronic device, and comprising communications circuitry (117) in the battery,

said digital, serial communication comprising transmission between said communications circuitry and the electronic device of bytes consisting of a number of bits, each bit being defined by one of a high level and a low level, wherein a leading bit (304) of each byte is of a first one of said high and low levels,

characterized in that said communications circuitry (117) is adapted to transmit the other of said high and low levels for a first period of time (404, 405) immediately prior to said leading bit.

17. An apparatus according to claim 16, characterized in that said communications circuitry comprises

means for transmitting each byte with a trailing bit (310) of the other of said high and low levels, and means for transmitting the other of said high and low levels for a second period of time (405, 406) immediately following said trailing bit.

18. An apparatus according to claim 17, characterized in that the sum of said first and second periods of time constitutes a waiting state between two consecutive bytes in the case where at least two bytes are transmitted following each other.

19. An apparatus according to claim 18, characterized in that said communications circuitry comprises means for changing the direction of transmission during said waiting state.

20. An apparatus according to claim 19, characterized in that said communications circuitry comprises means for retransmitting a byte, transmitted in one direction over said interface, in the opposite direction after the direction of transmission has been changed.

21. An apparatus according to claim 17, characterized in that said communications circuitry is adapted to assume an idle state wherein the first one of said high and low levels is transmitted, if said second period of time (406) has exceeded a preset value.

22. An apparatus according to claim 21, characterized in that said communications circuitry is adapted to assume a wake-up state defined by said first period of time (404) prior to receiving a byte as the first byte after an idle state.