Adaptation of standard microprocessor architectures via an interface to a configurable subsystem

• US 6,584,525 B1
• Filed: 11/19/1999
• Issued: 06/24/2003
• Est. Priority Date: 11/19/1998
• Status: Expired due to Term

• Current Assignee: SK Hynix Inc.
• Original Assignee: Edwin E. Klingman
• Inventors: Klingman, Edwin E.
• Primary Examiner(s): Myers, Paul R.
• Application Number:
  US09/443,944
• Time in Patent Office: 1,313 Days
• Field of Search: 710/118, 710/125, 710/305-315, 710/101
• US Class Current: 710/118
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)

Abstract

A system for extending standard processors using either undefined op-codes or sparse address spaces to maintain the use of legacy processor tools and reduce the complexity of the design process. The disclosure describes a method and apparatus for adding circuitry to processing units that allows partitioning of the design into a fixed processing unit derivative and a configurable subsystem. The legacy processor unit language tools work with the fixed processing unit derivative while the logic design tools work well with the configurable subsystem. In one embodiment, the configurable subsystem is implemented with easily available programmable Logic Devices (PLD'"'"'s and FPGA'"'"'s).

Claims

1. A processing system having an extended bus, the processing system comprising:

a central bus for carrying address, data and control signals relating to the address and data on the central bus;

having at least one I/O port, connected to the central bus, the I/O port forming the extended bus having address and data signals and control signals, including a select signal relating to the address and data signals on the extended bus; and

at least one functional unit connected to the central bus, the at least one functional unit having an inexhaustively decoded space, wherein use of an unassigned location in the space causes the activation of the select signal on the extended bus, wherein the functional unit includes an instruction processing unit for executing instructions and a register set residing in the inexhaustively decoded space, the instruction processing unit executing an instruction that references an unassigned location in the space to cause activation of the select signal; and

wherein data is transferable between the central bus and the extended bus when the select signal is activated on the extended bus.

2. A processing system having an extended bus as recited in claim 1, wherein an instruction that causes the activation of the select signal is a movx instruction.

3. A processing system having an extended bus as recited in claim 1,

further comprising an address decoder for the register set, the address decoder having an output and activating a signal on the output when the unassigned location is referenced, the select signal on the external bus being activated in response to the activated signal on the address decoder output.

4. A processing system having an extended bus as recited in claim 1,

further comprising an address decoder for the register set, the address decoder activating a signal on an output when the unassigned location is referenced;

and

wherein the instruction processing unit includes a timing and control unit that receives the address decoder output and activates a signal on an output in response to the activated signal on the address decoder output, the select signal on the external bus being activated in response to the activated signal on the timing and control unit output.

5. A processing system having an extended bus as recited in claim 1,

wherein the instruction processing unit includes a timing and control unit;

and

wherein the timing and control unit activates a signal on an output when the unassigned location is referenced the select signal on the external bus being activated in response to the activated signal on the timing and control unit output.

6. A processing system having an extended bus, the processing system comprising:

a central bus for carrying address, data and control signals relating to the address and data on the central bus;

at least one I/O port, connected to the central bus, the I/O port forming the extended bus having address and data signals and control signals, including a select signal relating to the address and data signals on the extended bus, wherein the control signals on the extended bus include a ready signal connected to the I/O port; and

at least one functional unit connected to the central bus, the at least one functional unit having an inexhaustively decoded space, wherein use of an unassigned location in the space causes activation of the select signal on the extended bus, wherein the functional unit includes an instruction processing unit, the processing unit receiving the ready signal from the I/O port, and an inactive state of the ready signal stalling the processing unit;

wherein data is transferable between the central bus and the extended bus when the select signal is activated on the extended bus.

7. A processing system having an extended bus, the processing system comprising:

a central bus for carrying address, data and control signals relating to the address and data on the central bus;

at least one I/O port, connected to the central bus, the I/O port forming the extended bus having address and data signals and control signals, including a select signal relating to the address and data signals on the extended bus; and

at least one functional unit connected to the central bus, the at least one functional unit having an inexhaustively decoded space, wherein use of an unassigned location in the space causes the activation of the select signal on the extended bus, wherein the functional unit includes an instruction processing unit for executing instructions residing in the inexhaustively decoded space, the instruction processing unit executing an instruction at an unassigned location in the inexhaustively decoded space to cause activation of the select signal; and

wherein data is transferable between the central bus and the extended bus when the select signal is activated on the extended bus.

8. A method of operating a processing system with an extended bus, the method comprising the steps of:

forming the extended bus from an I/O port connected to a central bus of the processing system, wherein the extended bus includes address data and control signals, including a select signal relating to the address and data signals on the extended bus;

executing an instruction in a functional unit, connected to the central bus of the processing system, and having an inexhaustively decoded space, the instruction using an unassigned location in the inexhaustively decoded space to cause activation of the select signal on the extended bus, wherein the functional unit includes an instruction processing unit and a register set residing in the inexhaustively decoded space, the instruction processing unit executing an instruction that makes a reference to an unassigned location of the space to cause activation of the select signal; and

transferring data between the central bus and the extended bus in response to executing the instruction causing the activation of the select signal.

9. A processing system having an extended bus as recited in claim 8,

wherein the functional unit further includes an address decoder for the register set, the address decoder having an output and activating a signal on the output when the unassigned location is referenced, the select signal on the external bus being activated in response to the activated signal on the address decoder output.

10. A processing system having an extended bus as recited in claim 8, wherein the instruction processing unit further includes a timing and control unit that activates a signal on an output when the unassigned location is referenced, the select signal on the external bus being activated in response to the activated signal on the timing and control unit output.

11. A method of operating a processing system with an extended bus, the method comprising the steps of:

forming the extended bus from an I/O port connected to a central bus of the processing system, wherein the extended bus includes address data and control signals, including a select signal relating to the address and data signals on the extended bus;

executing an instruction in a functional unit, connected to the central bus of the processing system, and having an inexhaustively decoded space, the instruction using an unassigned location in the inexhaustively decoded space to cause activation of the select signal on the extended bus, wherein the functional unit includes an instruction processing unit for executing instructions residing in the inexhaustively decoded space, the instruction processing unit executing an instruction at an unassigned location in the inexhaustively decoded space to cause activation of the select signal; and

transferring data between the central bus and the extended bus in response to executing the instruction causing the activation of the select signal.

12. A processing system having an extended bus, the processing system comprising:

a central bus for carrying address, data and control signals relating to the address and data on the central bus;

at least one I/O port, connected to the central bus, the I/O port forming the extended bus having address and data signals and control signals, including a select signal, relating to the address and data signals on the extended bus;

at least one functional unit connected to the central bus, the at least one functional unit having an inexhaustively decoded space, wherein use of unassigned location in the inexhaustively decoded space causes the activation of the select signal on the extended bus;

wherein data is transferable between the central bus and the extended bus when the select signal is activated on the extended bus; and

a configurable subsystem having an interface connected to the extended bus and activating the interface upon receiving an activated select signal, the configurable subsystem for implementing the functional extension.

13. A processing system having a functional extension as recited in claim 12, wherein the functional extension is a computational extension.

14. A processing system having a functional extension as recited in claim 12, wherein the functional extension is a I/O function extension.

15. A processing system having a functional extension as recited in claim 14, wherein the I/O function extension is a channel, the channel defining a group of contiguous addresses on the extended bus.

16. A processing system having a functional extension as recited in claim 12, wherein the configurable subsystem is a FPGA device.

17. A processing system having a functional extension as recited in claim 12, wherein the configurable subsystem is an ASIC device.

18. A processing system having an extended bus as recited in claim 12, wherein the unassigned location refers to the configurable subsystem connected to the extended bus.

19. A processing system having an extended bus as recited in claim 12, wherein use of the unassigned location further causes activation of one or more control signals on the extended bus, the activation of the one or more control signals on the extended bus defining the timing of the data transfer between the central bus and the extended bus.

20. A processing system having an extended bus as recited in claim 19, wherein one of the control signals is an address latch enable signal indicating the presence of an address on the extended bus.

21. A processing system having an extended bus as recited in claim 19, wherein one of the control signals is a write signal indicating the presence of write data on the extended bus.

22. A processing system having an extended bus as recited in claim 19, wherein one of the control signals is a read signal for capturing read data on the extended bus.

23. A processing system having an extended bus as recited in claim 19,

wherein the functional unit includes an instruction processing unit; and

wherein one of the control signals is a ready signal stalling the instruction processing unit during transfers on the extended bus.

24. A processing system having an extended bus, the processing system comprising:

a central bus for carrying address, data and control signals relating to the address and data on the central bus;

at least one I/O port, connected to the central bus, the I/O port forming the extended bus having address and data signals and control signals, including a select signal relating to the address and data signals on the extended bus; and

at least one functional unit connected to the central bus, wherein the functional unit includes an instruction processing unit for executing instructions and a register set residing in an inexhaustively decoded space, the instruction processing unit configured to execute an instruction that references an unassigned location in said space to cause activation of the select signal; and

wherein data is transferable between the central bus and the extended bus when the select signal is activated on the extended bus.

25. A processing system having an extended bus, the processing system comprising:

a central bus for carrying address, data and control signals relating to the address and data on the central bus;

at least one I/O port, connected to the central bus, the I/O port forming the extended bus having address and data signals and control signals, including a select signal relating to the address and data signals on the extended bus; and

means for processing, connected to the central bus, and including means for executing instructions and means for storing data, said storing means residing in an inexhaustively decoded space, wherein the means for executing institutions is configured to execute an instruction that references an unassigned location in said space to cause activation of the select signal; and

wherein data is transferable between the central bus and the extended bus when the select signal is activated on the extended bus.

26. A processing system having an extended bus, the processing system comprising:

a central bus for carrying address, data and control signals relating to the address and data on the central bus;

at least one I/O port, connected to the central bus, the I/O port forming the extended bus having address and data signals and control signals, including a select signal relating to the address and data signals on the extended bus; and

at least one functional unit connected to the central bus, wherein the functional unit includes an instruction processing unit for executing instructions in an instruction space, the instruction processing unit configured to execute an instruction at an unassigned location in the instruction space to cause activation of the select signal; and

wherein data is transferable between the central bus and the extended bus when the select signal is activated on the extended bus.

27. A processing system having an extended bus, the processing system comprising:

a central bus for carrying address, data and control signals relating to the address and data on the central bus;

at least one I/O port, connected to the central bus, the I/O port forming the extended bus having address and data signals and control signals, including a select signal relating to the address and data signals on the extended bus; and

means for processing, connected to the central bus, and including means for executing instructions in an instruction space, wherein the means for executing instructions is configured to execute an instruction at an unassigned location in the instruction space to cause activation of the select signal; and

wherein data is transferable between the central bus and the extended bus when the select signal is activated on the extended bus.

28. A method of operating a processing system with an extended bus, the method comprising the steps of:

forming the extended bus from an I/O port connected to a central bus of the processing system, wherein the extended bus includes address data and control signals, including a select signal relating to the address and data signals on the extended bus;

executing an instruction in a functional unit connected to the central bus of the processing system to cause activation of the select signal, wherein the functional unit includes an instruction processing unit and a register set residing in the inexhaustively decoded space, the instruction processing unit executing an instruction that makes a reference to an unassigned location of the space to cause activation of the select signal; and

transferring data between the central bus and the extended bus in response to executing the instruction causing activation of the select signal.

29. A method of operating a processing system with an extended bus, the method comprising the steps of:

forming the extended bus from an I/O port connected to a central bus of the processing system, wherein the extended bus includes address data and control signals, including a select signal relating to the address and data signals on the extended bus;

executing an instruction in a functional unit connected to the central bus of the processing system to cause activation of the select signal, wherein the functional unit includes an instruction processing unit for executing instructions residing in an instruction space, the instruction processing unit executing an instruction at an unassigned location in the instruction space to cause activation of the select signal; and

transferring data between the central bus and the extended bus in response to executing the instruction causing activation of the select signal.