Method and apparatus for invalidating data in a cache

• US 6,584,548 B1
• Filed: 07/22/1999
• Issued: 06/24/2003
• Est. Priority Date: 07/22/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Copeland, George Prentice, Bourne, Donald A., Claussen, Christopher Shane, McClain, Matthew Dale
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): Anderson, Matthew D.
• Application Number:
  US09/359,277
• Time in Patent Office: 1,433 Days
• Field of Search: 711/133, 711/134, 711/135, 711/136, 711/124, 711/128, 711/108, 711/144, 365/49
• US Class Current: 711/134
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means

Abstract

A data processing system comprising a cache memory, wherein a cache entry containing data is stored in the cache memory. A cache coordinator, wherein the cache coordinator invalidates one or more cache entries in response to a signal. An ID-based invalidation process, wherein a cache entry is associated with an ID that uniquely identifies the cache entry and can optionally be associated with one or more data ids that represent the underlying data contained in the cache entry, and the ID-based invalidation process sends a signal to the cache coordinator to invalidate all cache entries that either have that cache entry ID or have been associated with a data ID when the data that the ID represents changes. A time-limit-based invalidation process, wherein a cache entry can be associated with a time limit, and the time-limit-based invalidation process sends a signal to the cache coordinator to invalidate a cache entry whose time limit has expired. A URI-based invalidation process, wherein all cache entries generated by a template with that URI are invalidated when that template changes. A URI is a Universal Resource Identifier that identifies a template that generates different cache entries. For example, a product display template might have a URI named “productDisplay.jsp” that generate a page for each product. The present invention integrates all of these methods of invalidation into a single system.

Claims

1. A data processing system comprising:

a cache memory, wherein cache entries are stored in the cache memory;

a cache coordinator, wherein the cache coordinator invalidates cache entries in the cache memory in response to a signal;

a first ID-based invalidation process, wherein the first ID-based invalidation process sends a signal to the cache coordinator to invalidate a cache entry in the cache memory based on a cache entry ID;

a second ID-based invalidation process, wherein the second ID-based invalidation process sends a signal to the cache coordinator to invalidate cache entries in the cache memory based an associated data ID whose data changes; and

a time-limit-based invalidation process, wherein the time-limit-based invalidation process sends the signal to the cache coordinator to invalidate a cache entry in the cache memory in response to a presence of an expired time limit for the cache entry.

2. The data processing system of claim 1 further comprising:

a universal resource identifier based invalidation process, wherein the universal resource identifier based invalidation process sends the signal to the cache coordinator to invalidate a cache entry in the cache memory in response to a change in a template with that URI.

3. The data processing system of claim 1 further comprising:

an external cache adapter, wherein the cache coordinator, responsive to the cache entry being stored in an external cache, sends signals to the external cache to invalidate the cache entry through the external cache adapter.

4. The data processing system of claim 3 further comprising:

a server engine, wherein the server engine processes requests for pages and sends an invalidation signal to the cache coordinator.

5. The data processing system of claim 1, wherein the cache entry is invalidated in the cache memory by a template without directly using the cache coordinator.

6. The data processing system of claim 1, wherein a data structure is a database.

7. The data processing system of claim 1, wherein the cache memory, the cache coordinator, the first ID-based invalidation process, the second ID-based invalidation process, and the time-limit-based invalidation process are executed by a Java virtual machine.

8. The data processing system of claim 1, wherein the cache memory is located in a first Java virtual machine and the cache coordinator, the first ID-based invalidation process, the second ID-based invalidation process, and the time-limit-based invalidation process are located in a second Java virtual machine.

9. The data processing system of claim 1, wherein the data comprises a plurality of cache entries.

10. The data processing system of claim 1, wherein the second ID-based invalidation process sends the data ID as the signal.

11. The data processing system of claim 1, wherein the cache memory includes a plurality of cache entries and wherein the signal is the cache entry ID.

12. The data processing system of claim 1, wherein the signal originates from a template in the data processing system.

13. The data processing system of claim 1, wherein the cache memory contains a plurality of cache entries and wherein the cache coordinator associates cache entries in the cache memory using both the cache entry ID and at least zero data ids.