Method and system for booting a multiprocessor computer

• US 6,584,560 B1
• Filed: 04/19/2000
• Issued: 06/24/2003
• Est. Priority Date: 04/19/2000
• Status: Expired due to Term

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell USA LP (Dell Technologies Inc.)
• Inventors: Miller, Kevin Lee, Kroun, Jack, Martinez, Armando Jaime
• Primary Examiner(s): Butler, Dennis M.
• Assistant Examiner(s): Chang, Eric
• Application Number:
  US09/552,608
• Time in Patent Office: 1,161 Days
• Field of Search: 713/2, 713/1
• US Class Current: 713/2
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems

Abstract

A method and system for choosing the control processor for booting a multiprocessor system (10) in accordance with a memory (42). A computer system (10) includes a plurality of computer processors (12). The processors (12) use a memory bus (18) to communicate with the main memory (20). A second bus (30) connects the processors (12) to an interupt controller (34). The second bus (30) includes multiple bus request lines (14). An initialization control circuit (32) also communicates with the second bus (30). Memory (42) in the initialization control circuit (32) holds data identifying at least one of the processors (12) and when power is first provided to the system, the initialization control circuit (32) operates to assert signals on the bus request lines (14) such that the identified processor initializes the computer system.

Claims

1. A computer system, comprising:

a plurality of computer processors;

a first bus coupled to the computer processors and to at least one main memory;

a second bus coupled to the computer processors and an interrupt controller, and having a plurality of bus request lines;

a chipset coupled to the computer processors; and

an initialization control circuit coupled to the bus request lines and having a volatile memory, the volatile memory programmed by the chipset with data identifying at least one of the plurality of computer processors, the initialization control circuit operable to assert signals on the bus request lines such that the at least one computer processor identified in the memory initializes the computer system.

2. The computer system of claim 1, further comprising:

a plurality of local interrupt controllers, each coupled to at least one of the computer processors and to the second bus.

3. The computer system of claim 1, wherein each of the plurality of computer processors includes a local interrupt controller coupled to the second bus.

4. The computer system of claim 1, wherein the identified processor is the processor with the most limited feature set.

5. The computer system of claim 1, wherein the initialization control circuit includes data inputs and a write input for updating the memory.

6. The computer system of claim 1, wherein the identified processor is the current processor in a diagnostic sequence.

7. The computer system of claim 1, wherein the initialization control circuit is a programmable logic device.

8. A method for initializing a computer system, comprising the steps of:

providing power to a plurality of processors, a chipset and an initialization control circuit;

determining a bootstrap processor using the chipset;

programming a volatile memory of the initialization control circuit with data representing the bootstrap processor;

reading the bootstrap processor from the volatile memory of the initialization control circuit;

asserting a value on at least one bus request line connected to the processors, the value or values asserted corresponding to the bootstrap processor;

providing a first signal to the plurality of processors;

sampling the bus request lines in each processor in response to receiving the first signal; and

booting the system under the control of the bootstrap processor.

9. The method for initializing a computer system of claim 8, further comprising the steps of:

grouping the processors into a plurality of clusters; and

choosing a cluster; and

wherein the bootstrap processor is in the chosen cluster.

10. The method for initializing a computer system of claim 9, wherein each cluster includes an equal number of processors.

11. A method for programming an initialization control circuit, comprising the steps of:

providing power to a plurality of processors and an initialization control circuit;

determining an initial bootstrap processor by the hardware wiring of the processors to a bus;

detecting the presence of the remaining processors;

initializing the remaining processors;

building a multi processor table containing information including the family and model of the processors;

selecting a processor with the most limited features based on the information contained in the multi processor table; and

transferring data identifying the selected processor to a memory of an initialization control circuit.

12. The method for programming an initialization control circuit of claim 11, further comprising the steps of:

initializing the selected processor if the selected processor is not the initial bootstrap processor; and

transferring control to the selected processor if the selected processor is not the initial bootstrap processor.

13. The method for programming an initialization control circuit of claim 11, wherein the step of determining an initial bootstrap processor by the hardware wiring of the processors to a bus comprises:

asserting a first signal received by a first processor seated in a particular socket or slot;

designating the first processor as the initial bootstrap processor;

asserting a second signal on an output of the initial bootstrap processor;

receiving the second signal at bus request inputs of the remaining processors; and

designating the remaining processors as application processors.