JTAG port-sharing device

• US 6,584,590 B1
• Filed: 08/13/1999
• Issued: 06/24/2003
• Est. Priority Date: 08/13/1999
• Status: Expired due to Term

• Current Assignee: WSOU Investments, LLC (WSOU Holdings, LLC)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Bean, John R.
• Primary Examiner(s): Chung, Phung M.
• Application Number:
  US09/374,256
• Time in Patent Office: 1,411 Days
• Field of Search: 714/724, 714/733, 714/47, 714/30, 714/38, 714/35
• US Class Current: 714/724
• CPC Class Codes: G01R 31/318555 Control logic

Abstract

A JTAG port-sharing device that reduces the required number of hardware pins on an integrated circuit without limiting the integrated circuit testing to a particular debugging platform is provided. The JTAG port-sharing device eliminates the need to have individual hardware pins for each functional block that requires JTAG test interface and allows one set of hardware pins to be shared by a plurality of functional blocks. The JTAG port-sharing device is not limited by a particular debugging platform and allows the use of pre-owned and/or off-the-shelf testing software and/or JTAG debugger devices thereby leading to shorter development cycles and lower development costs.

Claims

1. A port-sharing device for testing an integrated circuit having a plurality of functional blocks, wherein the port-sharing device comprises:

(a) an equipment-under-test (EUT) interface port configured to be connected to a port on the integrated circuit; and

(b) at least two debugger ports, each configured to be connected to at least one debugger device to enable the at least one debugger device to test the plurality of functional blocks via the port on the integrated circuit.

2. The invention of claim 1, wherein the port-sharing device enables the debugger device to download a test program onto the integrated circuit via a corresponding debugger port and the EUT interface port.

3. The invention of claim 2, wherein the port-sharing device enables the debugger device to download the test program onto a particular functional block in the integrated circuit.

4. The invention of claim 1, wherein the port-sharing device enables the integrated circuit to upload test results onto the debugger device via the EUT interface port and a corresponding debugger port.

5. The invention of claim 1, wherein at least one debugger device is connected to two or more different debugger ports.

6. The invention of claim 1, wherein the port-sharing device emulates a direct connection between the debugger device and a corresponding functional block.

7. The invention of claim 6, wherein the port-sharing device further comprises:

(c) a processor configured to execute a program to emulate the direct connection; and

(d) a memory device for storing the program.

8. The invention of claim 7, wherein the program is stored as firmware on the memory device.

9. The invention of claim 1, wherein the port-sharing device is a Joint Test Action Group (JTAG) port-sharing device and the port on the integrated circuit comprises a pin.

10. The invention of claim 1, wherein:

the port-sharing device enables the debugger device to download a test program onto a particular functional block in the integrated circuit via a corresponding debugger port and the EUT interface port;

the port-sharing device enables the integrated circuit to upload test results onto the debugger device via the EUT interface port and the corresponding debugger port;

the port-sharing device emulates a direct connection between the debugger device and a corresponding functional block;

the port-sharing device further comprises;

(c) a processor configured to execute a program to emulate the direct connection; and

(d) a memory device for storing the program;

the program is stored as firmware on the memory device; and

the port-sharing device is a JTAG port-sharing device.

11. The invention of claim 10, wherein at least one debugger device is connected to two or more different debugger ports.

12. A method for testing an integrated circuit having a plurality of functional blocks, comprising the steps of:

(a) configuring an equipment-under-test (EUT) interface port of a port-sharing device to a port on the integrated circuit;

(b) configuring at least two debugger ports of the port-sharing device to be connected to at least one debugger device; and

(c) testing the plurality of function blocks in the integrated circuit with the at least one debugger device via the port-sharing device and via the port on the integrated circuit.

13. The invention of claim 12 wherein the port-sharing device enables the debugger device to download a test program onto the integrated circuit via a corresponding debugger port and the EUT interface port.

14. The invention of claim 13, wherein the port-sharing device enables the debugger device to download the test program onto a particular functional block in the integrated circuit.

15. The invention of claim 12, wherein the port-sharing device enables the integrated circuit to upload test results onto the debugger device via the EUT interface port and a corresponding debugger port.

16. The invention of claim 12 wherein at least one debugger device is connected to two or more different debugger ports.

17. The invention of claim 12 wherein the port-sharing device emulates a direct connection between the debugger device and a corresponding functional block.

18. The invention of claim 17, wherein the port-sharing device further comprises:

a processor configured to execute a program to emulate the direct connection; and

a memory device for storing the program.

19. The invention of claim 18, wherein the program is stored as firmware on the memory device.

20. The invention of claim 12, wherein the port-sharing device is a JTAG port-sharing device and the port on the integrated circuit comprises a pin.

21. The invention of claim 12, wherein:

the port-sharing device enables the debugger device to download a test program onto a particular functional block in the integrated circuit via a corresponding debugger port and the EUT interface port;

the port-sharing device enables the integrated circuit to upload test results onto the debugger device via the EUT interface port and the corresponding debugger port;

the port-sharing device emulates a direct connection between the debugger device and a corresponding functional block;

the port-sharing device further comprises;

a processor configured to execute a program to emulate the direct connection; and

a memory device for storing the program;

the program is stored as firmware on the memory device; and

the port-sharing device is a JTAG port-sharing device.

22. The invention of claim 21, wherein at least one debugger device is connected to two or more different debugger ports.