Accurate wafer patterning method for mass production

• US 6,586,143 B1
• Filed: 07/19/2000
• Issued: 07/01/2003
• Est. Priority Date: 07/19/2000
• Status: Expired due to Fees

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Tse, Tak Yan, Gn, Fang Hong, Tan, Juan Boon, Raphael, Sajan Marokkey
• Primary Examiner(s): GOUDREAU, GEORGE A
• Application Number:
  US09/619,359
• Time in Patent Office: 1,077 Days
• Field of Search: 430/5, 438/462, 438/692, 438/693, 216/89, 216/90
• US Class Current: 430/5
• CPC Class Codes: G03F 7/70425 Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
• CPC Class Codes: G03F 9/7084 Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for checking the position of alignment marks after a chemical mechanical polishing (CMP) process and automatically compensating for alignment of a wafer stepper based on the position checking is described. A wafer is provided having an alignment mark thereon for the purpose of aligning a reticle in the wafer stepper. The wafer is polished by CMP. Thereafter, alignment mark positioning is checked for deviation from a normal vectorial position of the alignment mark whereby information about the deviation is fed back to the wafer stepper and wherein the wafer stepper automatically compensates for correctable alignment error based on the deviation information.

Claims

1. A method of automatically compensating a wafer stepper for correctable alignment error in the fabrication of an integrated circuit device comprising:

providing a wafer having an alignment mark thereon for the purpose of aligning a reticle in said wafer stepper;

polishing said wafer;

thereafter checking for deviation of said alignment mark positioning from a normal vectorial position of said alignment mark whereby information about said deviation is fed back to said wafer stepper and wherein said wafer stepper automatically compensates for correctable alignment error.based on said deviation information;

depositing a thin film on said wafer; and

masking said wafer using said reticle in said wafer stepper.

2. The method according to claim 1 wherein any number of said alignment marks may be formed on said wafer and wherein the position of all of said alignment marks is checked.

3. The method according to claim 1 further comprising masking said wafer using said reticle in said wafer stepper after said step of checking for deviation of said alignment mark positioning.

4. The method according to claim 1 wherein said polishing step comprises chemical mechanical polishing.

5. The method according to claim 1 wherein said deviation information is also fed back to an operator of said polishing step.

6. A method of checking alignment mark positioning in the fabrication of an integrated circuit device comprising:

providing a wafer having an alignment mark thereon for the purpose of aligning a reticle in a stepper;

polishing said wafer;

thereafter checking for deviation of said alignment mark positioning from a normal vectorial position of said alignment mark whereby information about said deviation is fed back to said stepper and wherein said stepper automatically compensates for correctable alignment error based on said deviation information;

depositing a thin film on said wafer; and

masking said wafer using said reticle in said stepper.

7. The method according to claim 6 wherein any number of said alignment marks may be formed on said wafer and wherein the position of all of said alignment marks is checked.

8. The method according to claim 6 further comprising masking said wafer using said reticle in said stepper after said step of checking for deviation of said alignment mark positioning.

9. The method according to claim 6 wherein said polishing step comprises chemical mechanical polishing.

10. The method according to claim 6 wherein said deviation information is also fed back to an operator of said polishing step.

11. A method of checking alignment mark positioning after polishing in the fabrication of an integrated circuit device comprising:

providing a wafer having an alignment mark thereon for the purpose of aligning a reticle in a stepper;

polishing said wafer;

thereafter checking for deviation of said alignment mark positioning from a normal vectorial position of said alignment mark whereby information about said deviation is fed back to said stepper and wherein said stepper automatically compensates for correctable alignment error based on said deviation information;

thereafter depositing a thin film on said wafer;

masking said wafer using said reticle in said stepper to form a masking layer overlying said thin film; and

patterning said thin film using said masking layer to complete said fabrication of said integrated circuit device.

12. The method according to claim 11 wherein any number of said alignment marks may be formed on said wafer and wherein the position of all of said alignment marks is checked.

13. The method according to claim 11 wherein said polishing step comprises chemical mechanical polishing.

14. The method according to claim 11 wherein said deviation information is also fed back to an operator of said polishing step.

15. A method of automatically compensating a wafer stepper for correctable alignment error by checking alignment mark positioning after polishing in the fabrication of an integrated circuit device comprising:

providing a wafer having an alignment mark thereon for the purpose of aligning a reticle in said wafer stepper;

polishing said wafer using chemical mechanical polishing;

thereafter checking for deviation of said alignment mark positioning from a normal vectorial position of said alignment mark whereby information about said deviation is fed back to said wafer stepper and wherein said wafer stepper automatically compensates for correctable alignment error based on said deviation information;

depositing a thin film on said wafer; and

masking said wafer using said reticle in said wafer stepper.

16. The method according to claim 15 wherein any number of said alignment marks may be formed on said wafer and wherein the position of all of said alignment marks is checked.

17. The method according to claim 15 further comprising masking said wafer using said reticle in said wafer stepper after said step of checking for deviation of said alignment mark positioning.

18. The method according to claim 15 wherein said deviation information is also fed back to an operator of said polishing step.