Method of forming dual-metal gates in semiconductor device

• US 6,586,288 B2
• Filed: 10/18/2001
• Issued: 07/01/2003
• Est. Priority Date: 11/16/2000
• Status: Expired due to Term

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kim, Tae Kyun, Jang, Se Aug, Cha, Tae Ho, Lee, Jeong Youb
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LATTIN, CHRISTOPHER W
• Application Number:
  US09/982,841
• Publication Number:
  US 20020058374A1
• Time in Patent Office: 621 Days
• Field of Search: 438/183, 438/275-8
• US Class Current: 438/183
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A method of forming dual-metal gates in a semiconductor device, including the steps of providing a semiconductor substrate having a PMOS area and an NMOS area wherein dummy gates are formed in the PMOS and NMOS areas respectively, forming an insulating interlayer on the semiconductor substrate so as to cover the dummy gates, polishing the insulating interlayer until the dummy gates are exposed, forming a first groove defining a first metal gate area by selectively removing one of the dummy gates formed in the PMOS and NMOS areas, forming a first gate insulating layer and a first metal layer on an entire area of the semiconductor substrate including the first groove successively, forming a first metal gate in the first groove by etching the first metal layer and first gate insulating layer until the insulating interlayer is exposed, forming a second groove defining a second metal gate area by removing the remaining dummy gate, forming a second gate insulating layer and a second metal layer on the entire area of the semiconductor substrate including the second groove, and forming a second metal gate in the second groove by etching the second metal layer and second gate insulating layer until the insulating interlayer is exposed.

Claims

1. A method of forming dual-metal gates comprising the steps of:

providing a semiconductor substrate having a PMOS area and an NMOS area wherein dummy gates are formed in the PMOS and NMOS areas respectively;

forming an insulating interlayer on the semiconductor substrate so as to cover the dummy gates;

polishing the insulating interlayer until the dummy gates are exposed;

forming a first groove defining a first metal gate area by selectively removing one of the dummy gates formed in the PMOS and NMOS areas;

forming a first gate insulating layer and a first metal layer on an entire area of the semiconductor substrate including the first groove successively;

forming a first metal gate in the first groove by etching the first metal layer and first gate insulating layer until the insulating interlayer is exposed;

forming a second groove defining a second metal gate area by removing the remaining dummy gate;

forming a second gate insulating layer and a second metal layer on the entire area of the semiconductor substrate including the second groove; and

forming a second metal gate in the second groove by etching the second metal layer and second gate insulating layer until the insulating interlayer is exposed.

2. The method of claim 1, wherein the dummy gates are formed of stacked layers comprising oxide and doped polysilicon layers.

3. The method of claim 2, wherein the doped polysilicon layer is formed 2000 to 4000 Å

thick by LPCVD (low pressure chemical vapor deposition).

4. The method of claim 2, wherein the doped polysilicon layer is formed by dopant ion implantation or in-situ doping of dopant gas.

5. The method of claim 1, further comprising between the steps of forming the dummy gates and forming the insulating interlayer the following steps:

masking and lightly-doping ion implantation processes on the PMOS and NMOS areas in order;

depositing a nitride layer 900 to 1200 Å

thick on the semiconductor substrate including on the dummy gates;

forming spacers at both sidewalls of the dummy gates by blanket-etching the nitride layer; and

forming source/drain regions having lightly doped drain regions in the PMOS and NMOS areas below both lateral side extensions of the dummy gates including the spacers by carrying out masking and heavily-doping ion implantation processes on the PMOS and NMOS areas successively.

6. The method of claim 1, wherein the insulating interlayer is formed 5000 to 7000 Å

thick.

7. The method of claim 1, wherein the dummy gates are removed by dry etch or wet etch using mask oxide layers as etch barriers.

8. The method of claim 7, wherein the mask oxide layers are formed 500 to 800 Å

thick.

9. The method of claim 1, wherein the first and second gate insulating layers are formed by sequential deposition of an oxide layer, an oxynitride layer, and a high-k dielectric layer.

10. The method of claim 1, wherein the steps of etching the first and second metal layers and the first and second gate insulating layers are carried out by CMP (chemical mechanical polishing) or etch-back.

11. A method of forming dual-metal gates comprising the steps of:

providing a semiconductor substrate having a PMOS area and an NMOS area wherein dummy gates are formed in the PMOS and NMOS areas, respectively;

forming an insulating interlayer on the semiconductor substrate so as to cover the dummy gates;

polishing the insulating interlayer until the dummy gates are exposed;

forming first and second grooves defining first and second metal gate areas, respectively, by removing the dummy gates;

successively forming a gate insulating layer and a first metal layer on an entire area of the semiconductor substrate including on the first and second grooves;

selectively forming a metal nitride layer by carrying out nitridation on the first metal layer formed in one of the PMOS and NMOS areas;

forming a second metal layer on the metal nitride layer and the first metal layer so as to fill up the first and second grooves; and

forming first and second metal gates in the PMOS and NMOS areas, respectively, by etching the second metal layer, first metal layer, metal nitride layer, and gate insulating layer until the insulating interlayer is exposed.

12. The method of claim 11, wherein the gate insulating layer is formed by sequential deposition of an oxide layer, an oxynitride layer, and a high-k dielectric layer.

13. The method of claim 11, wherein the first metal layer is selectively formed of one of W, Ti, Ta, Mo, and Al.

14. The method of claim 13, wherein the first metal layer is formed 200 to 400 Å

thick by CVD.

15. The method of claim 11, wherein the nitridation is carried out by nitrogen ion implantation or by nitrogen plasma doping.

16. The method of claim 15, wherein the nitrogen ion implantation is carried out using N or N₂ as a dopant.

17. The method of claim 16, wherein the dopant of N is ion-implanted at an energy of 0.5 to 5 KeV and at a dose of 1×

10¹³ to 5×

10¹⁵ ions/cm².

18. The method of claim 16, wherein the dopant of N₂ is ion-implanted at an energy of 1 to 10 KeV and at a dose of 1×

10¹³ to 5×

10¹⁵ ions/cm².

19. The method of claim 15, wherein the nitrogen plasma doping is carried in ambient nitrogen, at an energy of 0.2 to 5 KeV, and at a dose of 1×

10¹³ to 5×

10¹⁵ ions/cm².

20. The method of claim 11, wherein the second metal layer is formed of a low-resistance metal layer 2000 to 5000 Å

thick.