Structure for ESD protection in semiconductor chips

• US 6,586,290 B1
• Filed: 06/15/1998
• Issued: 07/01/2003
• Est. Priority Date: 11/30/1995
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sher, Joseph C., Ma, Manny K. F., Casper, Stephen L.
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US09/097,481
• Time in Patent Office: 1,842 Days
• Field of Search: 438/24, 438/199, 438/200, 438/202, 438/316, 438/306, 438/305, 438/237, 438/232, 438/231, 438/228, 438/227, 438/224, 438/204, 438/210, 438/238, 257/358, 257/360
• US Class Current: 438/210
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps

Abstract

An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor. The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the transistor from ESD events. Metal conductors over the active areas, have a plurality of contacts to the active areas formed through an insulative layer to contact the active areas. Additional active areas adjacent to the active areas of the transistor are also coupled to the well resistors, and to a conductive layer which provides a conductor to the I/O pads. The active areas are silicided to reduce their resistance and increase the switching speed of the transistor. The n-well resistors are coupled in series to provide a large resistance with respect to that of the active areas to reduce the impact of ESD events.

Claims

1. A method of making an ESD protection device in a semiconductor substrate, comprising:

forming in the substrate first and second heavily doped active areas as a source and a drain of a lateral CMOS transistor;

forming in the substrate a third heavily doped area separated from the first active area;

forming a first well resistor between and at least partially under the first active area and the heavily doped third area and conductively coupled thereto, the first well resistor having a higher sheet resistance than the first active area and the third area;

forming in the substrate a first conductive layer disposed over the third area and electrically coupled thereto;

forming in the substrate a fourth heavily doped area separated from the second active area;

forming in the substrate a second well resistor formed between and at least partially under the second active area and the fourth heavily doped area and conductively coupled thereto, the second well resistor having a higher sheet resistance than the second active area and the fourth area; and

forming in the substrate a second conductive layer disposed over the fourth area and conductively coupled thereto.

2. A method of making an ESD protection device in a semiconductor substrate, comprising:

forming in the substrate first and second heavily doped active areas as a source and a drain of a lateral CMOS transistor;

forming in the substrate a third heavily doped area separated from the first active area;

forming a first well resistor between and at least partially under the first active area and the heavily doped third area and conductively coupled thereto, the first well resistor having a hither sheet resistance than the first active area and the third area;

forming in the substrate a first conductive layer disposed over the third area and electrically coupled thereto;

forming in the substrate a fourth heavily doped area separated from the second active area;

forming in the substrate a second well resistor formed between and at least partially under the second active area and the fourth heavily doped area and conductively coupled thereto, the second well resistor having a higher sheet resistance than the second active area and the fourth area;

forming in the substrate a second conductive layer disposed over the fourth area and conductively coupled thereto;

forming in the substrate a first insulative layer disposed between the third heavily doped area and the first conductive layer; and

forming in the substrate a first set of contacts electrically connecting the first conductive layer to the third area.

3. The method of claim 2, further comprising:

forming in the substrate a second insulative layer disposed between the fourth heavily doped area and the second conductive layer; and

forming in the substrate a second set of contacts electrically connecting the second conductive layer to the fourth area.

4. The method of claim 2, further comprising:

forming in the substrate a third conductive layer disposed over the first active area;

forming in the substrate a third insulative layer disposed between the first area and the first conductive layer; and

forming in the substrate a third set of contacts electrically coupling the third conductive layer to the first area.

5. The method of claim 3, further comprising:

forming in the substrate a fourth conductive layer disposed over the second active area;

forming in the substrate a fourth insulative layer disposed between the second area and the second conductive layer; and

forming in the substrate a fourth plurality of contacts electrically coupling the fourth conductive layer to the second area.

6. A method of making an ESD protection device in a semiconductor substrate, comprising:

forming in the substrate first and second heavily doped active areas as a source and a drain of a lateral CMOS transistor;

forming in the substrate a third heavily doped area separated from the first active area;

forming a first well resistor between and at least partially under the first active area and the heavily doped third area and conductively coupled thereto, the first well resistor having a higher sheet resistance than the first active area and the third area, wherein the first and second well resistors are doped with N type impurities;

forming in the substrate a first conductive layer disposed over the third area and electrically coupled thereto;

forming in the substrate a fourth heavily doped area separated from the second active area;

forming in the substrate a second well resistor formed between and at least partially under the second active area and the fourth heavily doped area and conductively coupled thereto, the second well resistor having a higher sheet resistance than the second active area and the fourth area; and

forming in the substrate a second conductive layer disposed over the fourth area and conductively coupled thereto.

7. The method of claim 6, wherein the second well resistor is disposed substantially in a straight line with the first well resistor.

8. The method of claim 7, wherein the transistor is also disposed substantially in the straight line.

9. The method of claim 6, further comprising forming in the substrate a first insulative layer disposed between the third heavily doped area and the first conductive layer.

10. The method of claim 6, further comprising forming in the substrate a first set of contacts electrically connecting the first conductive layer to the third area.

11. The method of claim 9, wherein the transistor is also disposed substantially in the straight line.

12. A method of making an ESD protection device in a semiconductor substrate, comprising:

forming in the substrate first and second heavily doped active areas as a source and a drain of a lateral CMOS transistor;

forming in the substrate a third heavily doped area separated from the first active area;

forming a first well resistor between and at least partially under the first active area and the heavily doped third area and conductively coupled thereto, the first well resistor having a higher sheet resistance than the first active area and the third area, wherein the first and second well resistors are doped with P type impurities;

forming in the substrate a first conductive layer disposed over the third area and electrically coupled thereto;

forming in the substrate a fourth heavily doped area separated from the second active area;

forming in the substrate a second well resistor formed between and at least partially under the second active area and the fourth heavily doped area and conductively coupled thereto, the second well resistor having a higher sheet resistance than the second active area and the fourth area; and

forming in the substrate a second conductive layer disposed over the fourth area and conductively coupled thereto.

13. The method of claim 12, wherein the second well resistor is disposed substantially in a straight line with the first well resistor.

14. The method of claim 12, further comprising forming in the substrate a first insulative layer disposed between the third heavily doped area and the first conductive layer.

15. The method of claim 12, further comprising forming in the substrate a first set of contacts electrically connecting the first conductive layer to the third area.

16. A method of making an ESD protection device in a semiconductor substrate, comprising:

forming in the substrate first and second heavily doped active areas as a source and a drain of a lateral CMOS transistor;

forming in the substrate a third heavily doped area separated from the first active area;

forming a first well resistor between and at least partially under the first active area and the heavily doped third area and conductively coupled thereto, the first well resistor having a higher sheet resistance than the first active area and the third area;

forming in the substrate a first conductive layer disposed over the third area and electrically coupled thereto;

forming in the substrate a fourth heavily doped area separated from the second active area;

forming in the substrate a second well resistor formed between and at least partially under the second active area and the fourth heavily doped area and conductively coupled thereto, the second well resistor having a higher sheet resistance than the second active area and the fourth area, wherein the second well resistor is disposed substantially in a straight line with the first well resistor; and

forming in the substrate a second conductive layer disposed over the fourth area and conductively coupled thereto.

17. The method of claim 16, wherein the transistor is also disposed substantially in the straight line.

18. A method of making an ESD protection device in a semiconductor substrate, comprising:

forming in the substrate first and second heavily doped active areas as a source and a drain of a lateral CMOS transistor;

forming in the substrate a third heavily doped area separated from the first active area;

forming a first well resistor between and at least partially under the first active area and the heavily doped third area and conductively coupled thereto, the first well resistor having a higher sheet resistance than the first active area and the third area;

forming in the substrate a first conductive layer disposed over the third area and electrically coupled thereto;

forming in the substrate a fourth heavily doped area separated from the second active area;

forming in the substrate a second well resistor formed between and at least partially under the second active area and the fourth heavily doped area and conductively coupled thereto, the second well resistor having a higher sheet resistance than the second active area and the fourth area;

forming in the substrate a second conductive layer disposed over the fourth area and conductively coupled thereto; and

treating the first and second active areas and the third and fourth heavily doped areas so as to lower their resistance.

19. The method of claim 18, wherein the treating step comprises siliciding the first and second active areas and the third and fourth heavily doped areas.

20. The method of claim 18, further comprising forming in the substrate a first insulative layer disposed between the third heavily doped area and the first conductive layer.

21. The method of claim 18, wherein the first and second well resistors are doped with N type impurities.

22. The method of claim 18, wherein the first and second well resistors are doped with P type impurities.

23. The method of claim 18, wherein the second well resistor is disposed substantially in a straight line with the first well resistor.

24. The method of claim 23, wherein the transistor is also disposed substantially in the straight line.

25. A method of making an ESD protection device in a semiconductor substrate, comprising:

forming in the substrate first and second heavily doped active areas as a source and a drain of a lateral CMOS transistor;

forming in the substrate a third heavily doped area separated from the first active area;

forming a first well resistor between and at least a partially under the first active area and the heavily doped third area and conductively coupled thereto, the first well resistor having a higher sheet resistance than the first active area and the third area;

forming in the substrate a first conductive layer disposed over the third area and electrically coupled thereto;

forming in the substrate a fourth heavily doped area separated from the second active area;

forming in the substrate a second well resistor formed between and at least partially under the second active area and the fourth heavily doped area and a conductively coupled thereto, the second well resistor having a higher sheet resistance than the second active area and the fourth area and disposed substantially in a straight line with the first well resistor;

forming in the substrate a second conductive layer disposed over the fourth area and conductively coupled thereto;

siliciding the first and second active areas and the third and fourth heavily doped areas so as to lower their resistance;

forming in the substrate a first insulative layer dispoed between the third heavily doped and the first conductive layer; and

forming in the substrate a first set pf contacts electrically connecting the first conductive layer to the third area.

26. The method of claim 25, wherein the first and second well resistors are doped with N type impurities.

27. The method of claim 25, wherein the first and second well resistors are doped with P type impurities.