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Spacer assisted trench top isolation for vertical DRAM's

  • US 6,586,300 B1
  • Filed: 04/18/2002
  • Issued: 07/01/2003
  • Est. Priority Date: 04/18/2002
  • Status: Expired due to Term
First Claim
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1. A method of forming a trench top isolation layer of a vertical dynamic random access memory (DRAM) device, comprising:

  • providing a workpiece, the workpiece comprising a substrate having a plurality of trenches formed therein, each trench having a top portion and a bottom portion, wherein a trench capacitor is formed in each trench bottom portion, the trench capacitors including an outer region and a inner region, each trench capacitor including a buried strap in the outer region and a capacitor inner plate in the inner region; and

    forming a trench top isolation (TTI) layer in the trench top portion over the trench capacitors, wherein the trench top isolation layer has a greater thickness over the capacitor inner region than over the capacitor outer region.

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