Spacer assisted trench top isolation for vertical DRAM's

• US 6,586,300 B1
• Filed: 04/18/2002
• Issued: 07/01/2003
• Est. Priority Date: 04/18/2002
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Hummler, Klaus M., Scholz, Arnd R.
• Primary Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US10/125,118
• Time in Patent Office: 439 Days
• Field of Search: 438/206, 438/242, 438/248, 438/282, 438/400, 438/404, 438/244, 438/240, 438/249, 438/386, 438/387, 438/392, 257/301, 257/296, 257/309, 257/330, 257/315, 257/333
• US Class Current: 438/242
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H10B 12/0387 Making the trench
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A trench top isolation (TTI) layer (148) and method of forming thereof for a vertical DRAM. A first assist layer (134) is disposed over trench sidewalls (133) and trench capacitor top surfaces (131). A second assist layer (136) is disposed over the first assist layer (134). The second assist layer (136) is removed from over the trench capacitor top surface (131), and the first assist layer (134) is removed from the trench capacitor top surface (131) using the second assist layer (136) as a mask. The second assist layer (136) is removed, and a first insulating layer (140) is disposed over the first assist layer (134) and trench capacitor top surface (131). A second insulating layer (142) is disposed over the first insulating layer (140), and the second insulating layer (142) is removed from the trench sidewalls (133). The first insulating layer (140) and the first assist layer (134) are removed from the trench sidewalls (133). The TTI layer (148) comprises the first and second insulating layer portions (146/144) that are left remaining over the trench capacitors (118). The TTI layer (148) has a greater thickness over the trench capacitor inner regions (152) than over the trench capacitor outer regions (150).

Claims

1. A method of forming a trench top isolation layer of a vertical dynamic random access memory (DRAM) device, comprising:

providing a workpiece, the workpiece comprising a substrate having a plurality of trenches formed therein, each trench having a top portion and a bottom portion, wherein a trench capacitor is formed in each trench bottom portion, the trench capacitors including an outer region and a inner region, each trench capacitor including a buried strap in the outer region and a capacitor inner plate in the inner region; and

forming a trench top isolation (TTI) layer in the trench top portion over the trench capacitors, wherein the trench top isolation layer has a greater thickness over the capacitor inner region than over the capacitor outer region.

2. The method according to claim 1, wherein forming the TTI layer comprises:

disposing a first insulating material over the trench capacitors; and

disposing a second insulating material over the first insulating material, wherein the second insulating material comprises a different material than the first insulating material.

3. The method according to claim 2, wherein disposing a first insulating material comprises disposing a nitride, and wherein disposing a second insulating material comprises disposing an oxide by high-density plasma (HDP).

4. The method according to claim 1, wherein the trenches comprise sidewalls and wherein the trench capacitors comprise a top surface, wherein forming a TTI layer comprises:

disposing a first assist layer over the trench sidewalls and trench capacitors;

disposing a second assist layer over the first assist layer;

removing the second assist layer from at least the trench capacitor top surface;

removing the first assist layer from at least the trench capacitor top surface using the second assist layer as a mask to leave a portion of the workpiece exposed proximate the trench capacitor top surface;

removing the second assist layer;

disposing a first insulating layer over the first assist layer and the trench capacitor top surface;

disposing a second insulating layer over the first insulating layer, the second insulating layer having a greater thickness over the trench capacitor top surface than on the trench sidewalls;

removing the second insulating layer from at least the trench sidewalls, leaving a portion of the second insulating layer over the first insulating layer; and

removing the first insulating layer and the first assist layer from the trench sidewalls, leaving a portion of the first insulating layer disposed over the trench capacitor top surfaces, wherein the remaining portions of the first and second insulating layer over the trench capacitor top surfaces form the TTI layer.

5. The method according to claim 4, wherein removing the first assist layer comprises:

removing a portion of the second assist layer from the trench sidewalls proximate the trench capacitor top surface; and

removing a portion of the first assist layer from beneath the second assist layer, proximate the exposed workpiece portions.

6. The method according to claim 4, wherein disposing the first assist layer comprises disposing a semiconductor material, wherein disposing the first insulating layer comprises disposing a nitride, and wherein disposing the second assist layer and second insulating layer comprise disposing an oxide.

7. The method according to claim 4, further comprising doping the exposed workpiece portions to form buried strap outdiffusion regions in the workpiece proximate the buried strap.

8. The method according to claim 1, further comprising forming an oxide layer on the workpiece, before forming the TTI layer.

9. A method of manufacturing a vertical dynamic random access memory (DRAM) device, comprising:

providing a workpiece, the workpiece including a substrate;

forming a plurality of trenches in the workpiece, each trench having a top portion, a bottom portion, and sidewalls;

forming a trench capacitor in each trench bottom portion, the trench capacitors having a top surface;

disposing a first assist layer over at least the trench sidewalls and trench capacitor top surfaces;

disposing a second assist layer over the first assist layer;

removing the second assist layer from over at least the trench capacitor top surface;

removing the first assist layer from at least the trench capacitor top surface using the second assist layer as a mask, leaving a portion of the workpiece at the trench sidewalls exposed proximate the trench capacitor top surface;

removing the second assist layer;

disposing a first insulating layer over at least the first assist layer and the trench capacitor top surface, the first insulating layer being conformal;

disposing a second insulating layer over the first insulating layer;

removing the second insulating layer from at least the trench sidewalls, leaving a portion of the second insulating layer over the trench capacitor top surface; and

removing the first insulating layer and the first assist layer from the trench sidewalls, leaving a portion of the first insulating layer disposed over the trench capacitor top surface, wherein the remaining portions of the first and second insulating layer form a trench top isolation (TTI) layer of the vertical DRAM device.

10. The method according to claim 9, wherein disposing the second insulating layer comprises disposing a second insulating layer having a greater thickness over the trench capacitor top surface than the thickness of the second insulating layer on the trench sidewalls.

11. The method according to claim 9, wherein removing the first assist layer comprises:

removing a portion of the second assist layer from the trench sidewalls proximate the trench capacitor top surface; and

removing a portion of the first assist layer from beneath the second assist layer, proximate the exposed workpiece portions.

12. The method according to claim 11, wherein the trench capacitors include an outer region and an inner region, the capacitors including a buried strap in the outer region and a capacitor inner plate in the inner region, further comprising:

doping the exposed workpiece portions to form buried strap outdiffusion regions in the workpiece proximate the buried strap.

13. The method according to claim 9, wherein disposing the first assist layer comprises disposing a semiconductor material, wherein disposing the first insulating layer comprises disposing a nitride, and wherein disposing the second assist layer and second insulating layer comprise disposing an oxide.

14. The method according to claim 9, further comprising depositing an oxide layer on the workpiece, before forming the TTI layer.

15. The method according to claim 9, further comprising:

forming a gate oxide over exposed portions of the trench sidewalls; and

disposing a semiconductor material over the trench top portion over the TTI layer to form a gate electrode.

16. The method according to claim 9, wherein the trench capacitors include an outer region and an inner region, wherein the TTI layer has a greater thickness over the capacitor inner region than over the capacitor outer region.

17. A method of processing a semiconductor device that includes at least one trench formed within a workpiece, the trench comprising sidewalls, the method comprising:

forming a first component within a bottom portion of the trench, leaving an upper portion of the trench exposed, the first component including a top surface;

forming a first sacrificial oxide over at least the trench sidewalls and the first component top surface;

disposing a first assist layer over the first sacrificial oxide, the first assist layer comprising a semiconductor material;

disposing a second assist layer over the first assist layer, the second assist layer comprising an oxide;

removing the second assist layer from at least over the first component top surface, leaving portions of the second assist layer remaining over the trench sidewalls;

using the second assist layer as a mask to remove the first assist layer from at least over the first component top surface, leaving the first assist layer over at least a portion of the trench sidewalls;

removing the second assist layer from the trench sidewalls;

depositing a first insulating material over the first assist layer and the first component top surface, the first insulating material comprising a nitride;

depositing a second insulating material over the first insulating material, the second insulating material comprising an oxide;

removing the second insulating material from at least the trench sidewalls; and

removing the first insulating material, and first assist layer from a top portion of the trench sidewalls, wherein the second insulating material and first insulating material remaining over the first component comprise a trench top isolation (TTI) layer.

18. The method according to claim 17, further comprising forming a second component in the trench upper portion.

19. The method according to claim 17, wherein removing the second assist layer comprises removing portions of the first sacrificial oxide from the trench sidewalls, further comprising:

doping exposed portions of the workpiece within the trenches, after removing the second assist layer and portions of the first sacrificial oxide from the trench sidewalls; and

forming a second oxide over at least the first component top surface and the trench sidewalls.

20. The method according to claim 17, wherein the semiconductor device comprises a vertical dynamic random access memory (DRAM), wherein the first component comprises a capacitor, and wherein the second component comprises a gate electrode.

21. The method according to claim 17, wherein the first component includes an outer region and an inner region, wherein the TTI layer has a greater thickness over the first component inner region than the thickness of the TTI layer over the first component outer region.