SEMICONDUCTOR-ON-INSULATOR TRANSISTOR, MEMORY CIRCUITRY EMPLOYING SEMICONDUCTOR-ON-INSULATOR TRANSISTORS, METHOD OF FORMING A SEMICONDUCTOR-ON-INSULATOR TRANSISTOR, AND METHOD OF FORMING MEMORY CIRCUITRY EMPLOYING SEMICONDUCTOR-ON-INSULATOR TRANSISTORS

• US 6,586,304 B2
• Filed: 06/24/1997
• Issued: 07/01/2003
• Est. Priority Date: 06/21/1996
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Prall, Kirk
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): VOCKRODT, JEFF B
• Application Number:
  US08/881,852
• Publication Number:
  US 20020048883A1
• Time in Patent Office: 2,198 Days
• Field of Search: 438/206, 438/311, 438/268, 438/270, 438/272, 438/386, 438/387, 438/212, 257/347, 257/296, 257/774, 257/330, 257/382, 257/750, 257/758, 257/760
• US Class Current: 438/268
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench

Abstract

The invention includes several aspects related to semiconductor-on-insulator transistors, to memory and other DRAM circuitry and arrays, to transistor gate arrays, and to methods of fabricating such constructions. In one aspect, a semiconductor-on-insulator transistor includes, a) an insulator layer; b) a layer of semiconductor material over the insulator layer; c) a transistor gate provided within the semiconductor material layer; and d) an outer elevation source/drain diffusion region and an inner elevation diffusion region provided within the semiconductor material layer in operable proximity to the transistor gate. In another aspect, DRAM circuitry includes a plurality of memory cells not requiring sequential access, at least a portion of the plurality having more than two memory cells for a single bit line contact. In still another aspect, a DRAM array of memory cells comprises a plurality of wordlines, source regions, drain regions, bit lines in electrical connection with the drain regions, and storage capacitors in electrical connection with the source regions; at least two drain regions of different memory cells being interconnected with one another beneath one of the wordlines. In yet another aspect, a DRAM array has more than two memory cells for a single bit line contact, and a plurality of individual memory cells occupy a surface area of less than or equal to 2f×(2f+f/N), where “f” is the minimum photolithographic feature size with which the array was fabricated, and “N” is the number of memory cells per single bit line contact within the portion.

Claims

1. A method of forming a semiconductor on insulator transistor comprising the following steps:

forming a semiconductor material layer on a substrate,

patterning a transistor gate line opening completely through the semiconductor material layer, the transistor gate line opening having opposing sidewalls;

forming a gate dielectric layer over the gate line opening sidewalls;

after forming the gate dielectric layer, filling the transistor gate line opening with electrically conductive material;

providing a channel region within the semiconductor material layer operably adjacent the transistor gate line opening; and

forming a pair of source/drain regions of the semiconductor-on-insulator transistor in operable proximity to the channel region by ion implanting of a conductivity enhancing impurity using two different masking steps to two different elevations within the semiconductor material layer, the drain region being formed on one of the sidewalls of the transistor gate line opening and not extending to below the transistor gate, there being no drain region on the other of the opposing sidewall of the transistor gate line opening.

2. The method of forming a semiconductor-on-insulator transistor of claim 1 wherein, after forming the gate dielectric layer, the electrically conductive material fills an entire remainder of the transistor gate line opening.

3. The method of forming a semiconductor-on-insulator transistor of claim 1 further comprising providing an etch stop layer outwardly of the semiconductor layer prior to providing the transistor gate line opening therein.

4. A method of forming a semiconductor-on-insulator transistor comprising the following steps:

forming a semiconductor material layer on a substrate;

patterning a transistor gate line opening within the semiconductor material layer, the transistor gate line opening having opposing sidewalls;

forming a gate dielectric layer over the gate line opening sidewalls;

after forming the gate dielectric layer, filling the transistor gate line opening with electrically conductive material;

providing a channel region within the semiconductor material layer operably adjacent the transistor gate line opening; and

forming a pair of source/drain regions of the semiconductor-on-insulator transistor within the semiconductor material layer in operable proximity to the channel region, the drain region being formed on one of the sidewalls of the transistor gate line opening and not extending to below the transistor gate, there being no drain region on the other of the opposing sidewall of the transistor gate line opening, one of the source/drain diffusion regions comprising an outer region, and the other of the source/drain diffusion regions comprising an inner diffusion region;

masking the semiconductor material layer to define a masked portion and an unmasked portion; and

ion implanting into the unmasked portion of the semiconductor material layer to form an electrically conductive plug contact to the inner diffusion region through the semiconductor material layer.

5. The method of forming a semiconductor-on-insulator transistor of claim 4 wherein the pair of source/drain regions are provided within the semiconductor material layer by ion implanting of a conductivity enhancing impurity to two different elevations within the semiconductor material layer.

6. The method of forming a semiconductor-on-insulator transistor of claim 4 wherein the pair of source/drain regions are provided within the semiconductor material layer by ion implanting of a conductivity enhancing impurity using two different masking steps to two different elevations within the semiconductor material layer.

7. The method of forming a semiconductor-on-insulator transistor of claim 4 wherein the gate line opening is provided completely through the semiconductor material layer.

8. The method of forming a semiconductor-on-insulator transistor of claim 4 wherein the gate line opening is provided only partially through the semiconductor material layer.

9. The method of forming a semiconductor-on-insulator transistor of claim 4 further comprising providing an etch stop layer outwardly of the semiconductor layer prior to providing the transistor gate line opening therein.

10. A method of forming a semiconductor-on-insulator transistor comprising the following steps:

forming a semiconductor material layer on a substrate;

patterning a transistor gate line opening within the semiconductor material layer, the transistor gate line opening having opposing sidewalls;

forming a gate dielectric layer over the gate line opening sidewalls;

after forming the gate dielectric layer, filling the transistor gate line opening with electrically conductive material;

providing a channel region within the semiconductor material layer operably adjacent the transistor gate line opening; and

after the filling the transistor gate line, forming a pair of source/drain regions of the semiconductor-on-insulator transistor in operable proximity to the channel region, the drain region being formed on one of the sidewalls of the transistor gate line opening and not extending to below the transistor gate, there being no drain region on the other of the opposing sidewall of the transistor gate line opening.

11. The method of forming a semiconductor-on-insulator transistor of claim 10 wherein the pair of source/drain regions are provided within the semiconductor material layer.

12. The method of forming a semiconductor-on-insulator transistor of claim 10 wherein the pair of source/drain regions are provided within the semiconductor material layer, the gate line opening being provided completely through the semiconductor material layer.

13. The method of forming a semiconductor-on-insulator transistor of claim 10 wherein the pair of source/drain regions are provided within the semiconductor material layer, the gate line opening being provided only partially through the semiconductor material layer.

14. The method of forming a semiconductor-on-insulator transistor of claim 10 wherein the gate line opening is provided completely through the semiconductor material layer.

15. The method of forming a semiconductor-on-insulator transistor of claim 10 wherein the gate line opening is provided only partially through the semiconductor material layer.

16. The method of forming a semiconductor-on-insulator transistor of claim 10 wherein the pair of source/drain regions are provided within the semiconductor material layer by ion implanting of a conductivity enhancing impurity to two different elevations within the semiconductor material layer.

17. The method of forming a semiconductor-on-insulator transistor of claim 10 wherein the pair of source/drain regions are provided within the semiconductor material layer by ion implanting of a conductivity enhancing impurity using two different masking steps to two different elevations within the semiconductor material layer.

18. The method of forming a semiconductor-on-insulator transistor of claim 10 further comprising providing an etch stop layer outwardly of the semiconductor layer prior to providing the transistor gate line opening therein.

19. A method of forming a semiconductor-on-insulator transistor comprising the following steps:

forming a semiconductor material layer on a substrate;

patterning a transistor gate line opening completely through the semiconductor material layer, the transistor gate line opening having opposing sidewalls;

forming a gate dielectric layer over the gate line opening sidewalls;

after forming the gate dielectric layer, filling the transistor gate line opening with electrically conductive material;

providing a channel region within the semiconductor material layer operably adjacent the transistor gate line opening; and

forming a pair of source/drain regions of the semiconductor-on-insulator transistor in operable proximity to the channel region by ion implanting of a conductivity enhancing impurity using two different masking steps to two different elevations within a singly formed portion of the semiconductor material layer, the drain region being formed on one of the sidewalls of the transistor gate line opening and not extending to below the transistor gate, there being no drain region on the other of the opposing sidewall of the transistor gate line opening.