Printed wiring board with controlled line impedance
First Claim
1. A printed wiring substrate comprising:
- a laminated printed wiring substrate having a patterned metal layer on a surface of the laminated printed wiring substrate, the patterned metal layer including a first pad;
a planarized dielectric layer disposed on the surface of the laminated printed wiring substrate and covering at least a portion of the first pad of the patterned metal layer, the planarized dielectric layer comprising a first dielectric layer portion proximate to the laminated printed wiring substrate, and a second dielectric layer portion disposed on the first dielectric layer portion;
a first via extending from an upper surface of the second dielectic layer portion of the planarized dielectric layer to the first pad;
a patterned thin-film metal layer formed on the planarized layer, a second pad of the patterned thin-film metal layer being electrically coupled to the first pad through the first via;
a third pad of the patterned thin-film metal layer, the third pad and the second pad being arranged with a pitch; and
a reference plane portion of the patterned thin-film metal layer, the reference plane portion disposed between the second pad and the third pad.
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Accused Products
Abstract
The present invention provides a solution to the problem of controlling the inter-layer impedance of a deposited thin film layer stack accommodating high-density interconnects. The invention enables high-density signal lines to be routed over a reference plane to achieve a desired characteristic impedance. In one embodiment, a first thin-film metal layer is formed on a planarized layer fabricated from multiple thin film dielectric layers. The reduced pad footprint in the first thin-film metal layer allows a major portion of the first thin-film metal layer to serve as a reference, or ground, plane to signal lines formed in a second thin-film metal layer that is separated from the first thin-film metal layer by a thin dielectric layer.
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Citations
21 Claims
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1. A printed wiring substrate comprising:
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a laminated printed wiring substrate having a patterned metal layer on a surface of the laminated printed wiring substrate, the patterned metal layer including a first pad;
a planarized dielectric layer disposed on the surface of the laminated printed wiring substrate and covering at least a portion of the first pad of the patterned metal layer, the planarized dielectric layer comprising a first dielectric layer portion proximate to the laminated printed wiring substrate, and a second dielectric layer portion disposed on the first dielectric layer portion;
a first via extending from an upper surface of the second dielectic layer portion of the planarized dielectric layer to the first pad;
a patterned thin-film metal layer formed on the planarized layer, a second pad of the patterned thin-film metal layer being electrically coupled to the first pad through the first via;
a third pad of the patterned thin-film metal layer, the third pad and the second pad being arranged with a pitch; and
a reference plane portion of the patterned thin-film metal layer, the reference plane portion disposed between the second pad and the third pad. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
wherein the reference plane portion is disposed between the third pad and the second pad for a length greater than about 70% of the pitch.
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5. The printed wiring substrate of claim 4 further comprising:
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a thin dielectric layer disposed on the patterned thin-film metal layer, the thin dielectric layer having a second via extending from a surface of the thin dielectric layer to the second pad; and
a second patterned thin-film metal layer disposed on the thin dielectric layer, a fourth pad of the second patterned thin-film metal layer being electrically coupled to the second pad through the second via.
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6. The printed wiring substrate of claim 5 further comprising:
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a second thin dielectric layer disposed on the second patterned thin-film metal layer; and
a third patterned thin-film metal layer.
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7. The printed wiring substrate of claim 6 wherein the third patterned thin-film metal layer includes a plurality of second signal lines, a second signal line of the plurality of second signal lines overlying the reference plane portion and having a second width, the second width being greater than the signal line width of the signal line of the second patterned thin-film metal layer, the second width being chosen to provide the second signal line with the selected characteristic impedance.
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8. The printed wiring substrate of claim 5 wherein the thin dielectric layer is a polymer material having a thickness less than or equal to about 10 microns.
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9. The printed wiring substrate of claim 1 wherein the second patterned metal layer is a pattern-plated layer having a thickness of less than about 10 microns.
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10. The printed wiring substrate of claim 9 wherein the thin-film metal layer is a sputtered metal layer.
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11. The printed wiring substrate of claim 1 wherein the planarized dielectric layer is about 90% planarized with a step topology less than about 2 microns.
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12. A printed wiring substrate comprising:
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a laminated printed wiring substrate having a patterned metal layer on a surface of the laminated printed wiring substrate, the patterned metal layer including a first pad having a first minimum diameter;
a planarized layer disposed on the surface of the laminated printed wiring substrate and covering at least a portion of the first pad of the patterned metal layer, the planarized layer including a second layer portion disposed on a first layer portion and having a surface step topology of less than about 2 microns, a first via extending from the surface of the planarized layer to the first pad;
a first patterned thin-film metal layer having a first thickness of less than about 5 microns formed on the planarized layer, the first patterned thin-film metal layer including a reference plane portion and a second pad, the second pad of the first patterned thin-film metal layer being electrically coupled to the first pad through the first via;
a first dielectric layer having a first selected thickness equal to or less than about 10 microns disposed on the first patterned thin-film metal layer, the first dielectric layer having a second via extending from a surface of the first dielectric layer to the second pad; and
a second patterned thin film metal layer formed on the first dielectric layer, the second patterned metal having a plurality of signal lines disposed over the reference plane portion such that at least about 70% of the plurality of signal lines have a characteristic impedance within about 10% of a selected design impedance.
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13. A printed wiring substrate comprising:
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a laminated printed wiring substrate having a patterned metal layer on a surface of the laminated printed wiring substrate;
a planarized layer disposed on the surface of the laminated printed wiring substrate and covering at least a portion of the patterned metal layer, the planarized layer having a surface step topography of equal to or less than about 2 microns;
a first patterned thin-film metal layer disposed above the surface of the laminated printed wiring substrate;
a second patterned thin-film metal layer disposed above the surface of the laminated printed wiring substrate; and
a dielectric layer disposed between the first patterned thin-film layer and the second patterned thin-film layer, wherein one of the first patterned thin-film metal layer and the second patterned thin-film metal layer has a ground plane and a pad, the other of the first patterned thin film metal layer and the second patterned thin-film metal layer includes a plurality of signal lines, at least about 55% of the signal lines having a characteristic impedance within about 10% of a design impedance, the design impedance being about 28-50 ohms.
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14. A printed wiring substrate comprising:
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a laminated printed wiring substrate having a patterned metal layer on a surface of the laminated printed wiring substrate, the patterned metal layer including a first pad;
a planarized layer disposed on the surface of the laminated printed wiring substrate and covering at least a portion of the first pad of the patterned metal layer, a first via extending from a surface of the planarized layer to the first pad;
a patterned thin-film metal layer formed on the planarized layer, a second pad of the patterned thin-film metal layer being electrically coupled to the first pad through the first via;
a third pad of the patterned thin-film metal layer, the third pad and the second pad being arranged with a pitch;
a reference plane portion of the patterned thin-film metal layer, the reference plane portion disposed between the second pad and the third pad;
a thin dielectric layer disposed on the patterned thin-film metal layer, the thin dielectric layer having a second via extending from a surface of the thin dielectric layer to the second pad; and
a second patterned thin-film metal layer disposed on the thin dielectric layer, a fourth pad of the second patterned thin-film metal layer being electrically coupled to the second pad through the second via;
wherein the third pad and the second pad are ranged with a pitch; and
wherein the reference plane portion is disposed between the third pad and the second pad for a length greater than about 70% of the pitch; and
wherein the second patterned thin-film metal layer includes a plurality of signal lines, a signal line of the plurality of signal lines overlying the reference plane portion and having a signal line width, wherein a thickness of the thin dielectric layer is chosen according to the signal line width and a dielectric constant of a dielectric material comprising the thin dielectric layer to achieve a selected characteristic impedance of the signal line, and wherein at least about 70% of the plurality of signal lines have an impedance within about 10% of the selected characteristic impedance. - View Dependent Claims (15)
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16. A printed wiring substrate comprising:
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a laminated printed wiring substrate having a patterned metal layer on a surface of the laminated printed wiring substrate, the patterned metal layer including a first pad;
a planarized dielectric layer disposed on the surface of the laminated printed wiring substrate and covering at least a portion of the first pad of the patterned metal layer, a first via extending from a surface of the planarized dielectric layer to the first pad;
a patterned thin-film metal layer formed on the planarized dielectric layer, a second pad of the patterned thin-film metal layer being electrically coupled to the first pad through the first via;
a third pad of the patterned thin-film metal layer, the third pad and the second pad being arranged with a pitch; and
a reference plane portion of the patterned thin-film metal layer, the reference plane portion disposed between the second pad and the third pad;
wherein the third pad and the second pad are arranged with a pitch; and
wherein the reference plane portion is disposed between the third pad and the second pad for a length greater than about 70% of the pitch. - View Dependent Claims (17, 18, 19, 20)
a thin dielectric layer disposed on the patterned thin-film metal layer, the thin dielectric layer having a second via extending from a surface of the thin dielectric layer to the second pad; and
a second patterned thin-film metal layer disposed on the thin dielectric layer, a fourth pad of the second patterned thin-film metal layer being electrically coupled to the second pad through the second via.
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18. The printed wiring substrate of claim 17 further comprising:
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a second thin dielectric layer disposed on the second patterned thin-film metal layer; and
a third patterned thin-film metal layer.
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19. The printed wiring substrate of claim 18 wherein the third patterned thin-film metal layer includes a plurality of second signal lines, a second signal line of the plurality of second signal lines overlying the reference plane portion and having a second width, the second width being greater than the signal line width of the signal line of the second patterned thin-film metal layer, the second width being chosen to provide the second signal line with the selected characteristic impedance.
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20. The printed wiring substrate of claim 17 wherein the thin dielectric layer is a polymer material having a thickness less than or equal to about 10 microns.
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21. A printed wiring substrate comprising:
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a laminated printed wiring substrate having a patterned metal layer on a surface of the laminated printed wiring substrate, the patterned metal layer including a first pad;
a planarized dielectric layer disposed on the surface of the laminated printed wiring substrate and covering at least a portion of the first pad of the patterned metal layer, a first via extending from a surface of the planarized dielectric layer to the first pad;
a patterned thin-film metal layer formed on the planarized dielectric layer, a second pad of the patterned thin-film metal layer being electrically coupled to the first pad through the first via;
a third pad of the patterned thin-film metal layer, the third pad and the second pad being arranged with a pitch; and
a reference plane portion of the patterned thin-film metal layer, the reference plane portion disposed between the second pad and the third pad;
wherein the planarized dielectric layer is about 90% planarized with a step topology less than about 2 microns.
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Specification