Aerosol silicon nanoparticles for use in semiconductor device fabrication

• US 6,586,785 B2
• Filed: 06/29/2001
• Issued: 07/01/2003
• Est. Priority Date: 06/29/2000
• Status: Expired due to Term

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Ostraat, Michele L., Bell, Lloyd D. II, Boer, Elizabeth, Atwater, Harry A., Flagan, Richard C.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Tran, Mai-Huong
• Application Number:
  US09/895,790
• Publication Number:
  US 20020074565A1
• Time in Patent Office: 732 Days
• Field of Search: 257/77, 257/314, 257/321, 257/407, 257/412, 257/741, 438/503, 438/507, 438/509
• US Class Current: 257/261
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 2216/06 Floating gate cells in which the floating gate consists of multiple isolated silicon islands, e.g. nanocrystals
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors

Abstract

A stratum or discontinuous monolayer of dielectric-coated semiconductor particles includes a high density of semiconductor nanoparticles with a tightly controlled range of particle sizes in the nanometer range. In an exemplary embodiment, the nanoparticles of the stratum are substantially the same size and include cores which are crystalline, preferably single crystalline, and include a density which is approximately the same as the bulk density of the semiconductor material of which the particle cores are formed. In an exemplary embodiment, the cores and particles are preferably spherical in shape. The stratum is characterized by a uniform particle density on the order of 10¹² to 10¹³ particles/cm². A plurality of adjacent particles contact each other, but the dielectric shells provide electrical isolation and prevent lateral conduction between the particles of the stratum. The stratum includes a density of foreign atom contamination of less than 10¹¹ atoms/cm². The stratum is advantageously used as the floating gate in a non-volatile memory device such as a MOSFET. The non-volatile memory device including the discontinuous floating gate of semiconductor nanoparticles exhibits excellent endurance behavior and long-term non-volatility.

Claims

1. A semiconductor device comprising a stratum formed of a plurality of discrete particles, each of said particles having a core formed of one of metal and semiconductor material and being enveloped by a continuous dielectric coating formed on a surface thereof, the majority of said cores of said particles formed of a single crystalline material and including a density substantially as great as the bulk density of the material of which said cores are formed.

2. The semiconductor device as in claim 1, in which said particles of said stratum are arranged substantially in a monolayer.

3. The semiconductor device as in claim 1, in which said particles are substantially the same size.

4. The semiconductor device as in claim 1, in which said stratum includes a density of said particles within the range of about 10¹²-10¹³ particles/cm².

5. The semiconductor device as in claim 1, in which a plurality of adjacent particles contact each other.

6. The semiconductor device as in claim 1, in which said cores are substantially spherical.

7. The semiconductor device as in claim 1, in which said particles include silicon cores.

8. The semiconductor device as in claim 7, in which said silicon cores have an average diameter within a range of 3-7 nanometers.

9. The semiconductor device as in claim 7, in which said silicon cores are single crystalline silicon.

10. The semiconductor device as in claim 1, in which at least 90 percent of said cores have a diameter within the range of 2-10 nanometers.

11. The semiconductor device as in claim 1, in which said cores occupy approximately 30-75 percent of the volume of said discrete particles.

12. The semiconductor device as in claim 1, in which said particles include a distribution of particle diameters that is approximately log-normal, and said distribution includes a geometric standard deviation of less than 1.5.

13. The semiconductor device as in claim 1, wherein said dielectric coating comprises an oxide coating.

14. The semiconductor device as in claim 1, in which each of said cores is crystalline.

15. The semiconductor device as in claim 1, characterized by said stratum including a foreign particle contamination level being less than 10¹¹ atoms/cm².

16. The semiconductor device as in claim 1, in which said dielectric coating includes a thickness ranging from 1.5-2.0 nanometers.

17. A semiconductor device comprising a floating gate transistor including a tunnel oxide, a stratum of discrete nanoparticles formed over said tunnel oxide, and an upper gate oxide formed over said stratum, said stratum comprising a plurality of electrically isolated discrete crystallized nanoparticles, a majority of said nanoparticles being single crystalline, and each of said nanoparticles having a density substantially as great as the bulk density of the material of which said nanoparticles are formed and being enveloped by a continuous dielectric coating formed on a surface thereof.

18. The semiconductor device as in claim 17, wherein said nanoparticles comprise silicon nanoparticles.

19. The semiconductor device as in claim 17, in which each nanoparticle includes an oxide shell and in which a plurality of adjacent nanoparticles contact each other.

20. The semiconductor device as in claim 17, in which said nanoparticles have an average diameter within the range of 2-6 nanometers.

21. The semiconductor device as in claim 17, in which at least 90 percent of said nanoparticles include a diameter within the range of 2 to 6 nanometers.

22. The semiconductor device as in claim 17, in which said tunnel oxide includes a thickness within the range of 3-6 nanometers.

23. The semiconductor device as in claim 17, in which said floating gate transistor includes a gate width within the range of 0.18 microns to 1.2 microns.

24. The semiconductor device as in claim 17, in which said upper gate oxide includes a thickness within a range of 6-15 nanometers.

25. The semiconductor device as in claim 18, in which said stratum includes said discrete silicon nanoparticles having a density within a range of 10¹² to 10¹³ nanoparticles/cm².

26. The semiconductor device as in claim 18, in which said floating gate transistor includes a gate width and said discrete silicon nanoparticles include an average diameter being no greater than 0.1 of said gate width.

27. The semiconductor device as in claim 17, in which said gate width is less than or equal to 0.2 microns.

28. The semiconductor device as in claim 17, in which said floating gate transistor has a threshold voltage window of at least 2 volts.

29. The semiconductor device as in claim 17, in which said floating gate transistor includes a threshold voltage of about 3.3 volts when programmed and a threshold voltage of about 1 volt when erased.

30. The semiconductor device as in claim 17, in which said floating gate transistor is characterized by less than a 15% V_t window closure after 5×

10⁵ program/erase cycles.

31. The semiconductor device as in claim 17, in which said plurality of discrete nanoparticles are characterized as having a distribution of particle sizes that is approximately log-normal, and said distribution includes a geometric standard deviation of less than 1.5.