Semiconductor device having breakdown voltage limiter regions

• US 6,586,801 B2
• Filed: 05/01/2001
• Issued: 07/01/2003
• Est. Priority Date: 05/01/2000
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Sato, Takahiro, Onishi, Yasuhiko, Iwamoto, Susumu, Fujihira, Tatsuhiko
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Lewis, Monica
• Application Number:
  US09/845,747
• Publication Number:
  US 20010052601A1
• Time in Patent Office: 791 Days
• US Class Current: 257/339
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A semiconductor device facilitates preventing hot carriers from being injected into the insulation film so that the characteristics and the reliability of the active region thereof may not be impaired. The device includes an alternating-conductivity-type drain including heavily doped p-type breakdown voltage limiter regions in the portions of p-type partition regions in contact with the well bottoms of p-type base regions. Since the electric field in the central portion of breakdown voltage limiter regions reaches the critical value in advance to the electric field at the points E beneath gate insulation films the electric field at the points E is relaxed and hot carrier injection into gate insulation films is prevented.

Claims

1. A semiconductor device comprising:

a semiconductor chip having a first major surface and a second major surface facing opposite to the first major surface;

a first main electrode on the first major surface;

a second main electrode on the second major surface;

an active region in electrical contact with the first main electrode; and

a layer with low electrical resistance in electrical contact with the second main electrode;

an alternating-conductivity-type drain drift layer between the active region and the layer with low electrical resistance;

wherein the alternating-conductivity-type drain drift layer comprises first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type;

wherein the first semiconductor regions and the second semiconductor regions are arranged alternately with each other; and

wherein the alternating-conductivity-type drain drift layer further includes breakdown voltage limiter regions of the second conductivity type in the second semiconductor regions having a higher impurity concentration than adjacent portions of the first conductivity type in the first semiconductor regions.

2. The semiconductor device according to claim 1, wherein an impurity concentration in the breakdown voltage limiter region is higher than the impurity concentration of the first conductivity type in the first semiconductor region.

3. The semiconductor device according to claim 1, wherein the width of the breakdown voltage limiter region is wider than the width of the first semiconductor region.

4. The semiconductor device according to claim 1, wherein each of the first and second semiconductor regions forms a stripped area, the first and the second semiconductor regions are laminated of the striped areas of the first semiconductor regions, and the striped areas of the second semiconductor regions arranged alternately.

5. The semiconductor device according to claim 1, wherein the first semiconductor regions and the second semiconductor regions each are column shaped and arranged at respective lattice points thereof.

6. The semiconductor device according to claim 1, wherein the first semiconductor regions or the second semiconductor regions are shaped with walls forming a honeycomb.

7. The semiconductor device according to claim 1, wherein the active region constitutes a double-diffused MOSFET structure.

8. The semiconductor device according to claim 1, wherein the first semiconductor regions and the second semiconductor regions extend vertically and are arranged alternately side by side.

9. The semiconductor device according to claim 1, wherein an impurity concentration in the breakdown voltage limiter regions in the second semiconductor regions is higher than the impurity concentration of remaining portions of the second semiconductor regions.

10. The semiconductor device according to claim 1, wherein the width of the breakdown voltage limiter regions is wider than remaining portions of the second semiconductor regions.