Vacuum package fabrication of integrated circuit components

• US 6,586,831 B2
• Filed: 08/10/2001
• Issued: 07/01/2003
• Est. Priority Date: 02/02/2000
• Status: Expired due to Term

• Current Assignee: L-3 Communications Corporation (L3Harris Technologies, Inc.)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Gooch, Roland W., Schimert, Thomas R.
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Ortiz, Edgardo
• Application Number:
  US09/928,031
• Publication Number:
  US 20020000646A1
• Time in Patent Office: 690 Days
• Field of Search: 257/666, 257/667, 257/668, 257/787, 257/788, 257/789, 257/704, 257/723, 228/124, 228/217, 228/221, 438/107
• US Class Current: 257/704
• CPC Class Codes: B81B 7/0077 Other packages not provided for in groups B81B7/0035 - B81B7/0074
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/909 Controlled atmosphere

Abstract

A vacuum package for integrated circuit devices includes a sealing ring having multiple control spacers of uniform thickness distributed around the sealing ring. The sealing ring is in a designated area on a substrate, material and surrounds one or more integrated circuit devices. The vacuum package also includes a sealing layer on the sealing ring. A vacuum package lid is sealed to the sealing ring by the sealing layer on the sealing ring. The vacuum package lid provides a vacuum cell for the one or more integrated circuit devices.

Claims

1. A vacuum package containing one or more integrated circuit devices, comprising:

one or more integrated circuit devices formed on a device wafer, said devices having one or more associated bonding pads;

a sealing ring formed on the device wafer between the perimeter of the one or more integrated circuit devices and the one or more bonding pads coupled to the one or more integrated circuit devices;

a plurality of uniform thickness control spacers formed as part of and distributed around the sealing ring; and

a vacuum package lid sealed to the sealing ring, the vacuum package lid uniformly spaced from the device wafer by the control spacers thereby providing a vacuum cell for the one or more integrated circuit devices.

2. The vacuum package of claim 1, wherein the vacuum package lid includes a pressure level cavity formed within the sealing ring for increasing the volume of the vacuum cell and for decreasing the pressure level within the vacuum cell.

5. The vacuum package of claim 1, wherein the plurality of spacers comprise silicon nitride.

6. The vacuum package of claim 1, wherein the plurality of spacers are formed from the substrate material.

3. A vacuum package for integrated circuit devices, comprising:

a sealing ring having a plurality of uniform thickness control spacers distributed around the sealing ring, the sealing ring in a designated area on a substrate material, the sealing ring surrounding one or more integrated circuit devices;

a sealing layer on the sealing ring; and

a vacuum package lid sealed to the sealing ring by the sealing layer on the sealing ring, the vacuum package lid providing a vacuum cell for the one or more integrated circuit devices.

4. The vacuum package of claim 3, further comprising:

a dielectric layer formed on the area designated as the sealing ring.

7. The vacuum package of claim 3, wherein the sealing layer comprises an indium compression seal.

8. The vacuum package of claim 3, wherein the sealing layer comprises a solder layer.

9. A vacuum package containing a plurality of integrated circuit devices, comprising:

a plurality of integrated circuit devices formed in a pattern on a device wafer, said circuit devices each having one or more associated bonding pads;

a plurality of sealing rings formed on the device wafer, each sealing ring surrounding one or more of the plurality of integrated circuit devices between the perimeter of the one or more integrated circuit devices and one or more bonding pads coupled to the surrounding one or more integrated circuit devices;

a plurality of uniform thickness control spacers formed as part of and distributed around each of the plurality of sealing rings; and

a vacuum package lid for providing a plurality of vacuum cells, a vacuum cell for each of the one or more integrated circuit devices surrounded by one of the plurality of sealing rings, the vacuum package lid uniformly spaced from the device wafer by the control spacers and sealing to the plurality of sealing rings.

10. The vacuum package of claim 9 wherein the vacuum package lid comprises a plurality of second sealing rings corresponding to the plurality of sealing rings formed on the device wafer.

11. The vacuum package of claim 9 wherein the vacuum package lid comprises a plurality of pressure level cavities, each cavity formed in the package lid within one of the second sealing rings.

12. The vacuum package of claim 9 further comprising a sealing layer formed on each of the plurality of sealing rings formed on the device wafer.

13. The vacuum package of claim 10 further comprising a sealing layer formed on each of the plurality of second sealing rings formed on the vacuum package lid.

14. The vacuum package of claim 9 wherein the pattern of the plurality of integrated circuit devices comprises rows and columns further comprising:

bonding pad channels formed in the vacuum package lid in an orientation to correspond with the bonding pads to provide bonding pad clearance.

15. The vacuum package of claim 10, further comprising:

an anti-reflective coating on the inner surface of the vacuum package lid within each of the second sealing rings.