Packaged power devices having vertical power mosfets therein that are flip-chip mounted to slotted gate electrode strip lines

• US 6,586,833 B2
• Filed: 11/05/2001
• Issued: 07/01/2003
• Est. Priority Date: 11/16/2000
• Status: Expired due to Term

• Current Assignee: Silicon Semiconductor Corporation
• Original Assignee: Silicon Semiconductor Corporation
• Inventors: Baliga, Bantval Jayant
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Lewis, Monica
• Application Number:
  US09/992,233
• Publication Number:
  US 20020056872A1
• Time in Patent Office: 603 Days
• Field of Search: 257/68, 257/71, 257/295-313, 257/275, 257/691, 257/728, 257/732, 257/220, 257/249, 257/242, 257/263, 257/302, 257/304, 257/311, 257/328-331, 257/712, 257/678, 257/692, 257/699, 333/247
• US Class Current: 257/712
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/371 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/40095 Kinked
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/73255 Bump and strap connectors
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/84 using a strap connector
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/37 of an individual strap connector
• CPC Class Codes: H01L 24/40 of an individual strap connector
• CPC Class Codes: H01L 24/41 of a plurality of strap connectors
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0696 : of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/402 : Field plates
• CPC Class Codes: H01L 29/407 : Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 : for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/66712 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 : structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13063 : Metal-Semiconductor Field-Effect Transistor [MESFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/1903 : including wave guides
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

Packaged power devices include an electrically conductive flange having a slot therein and an electrically conductive substrate mounted within the slot. A dielectric layer is provided on the electrically conductive substrate and a gate electrode strip line is patterned on the dielectric layer. The gate electrode strip line extends opposite the electrically conductive substrate. A vertical MOSFET is also provided. The vertical MOSFET has a source electrically coupled and mounted to a first portion of the flange located outside the slot and a gate electrode electrically coupled and mounted to a first end of the gate electrode strip line.

Claims

1. A packaged power device, comprising:

an electrically conductive flange having a slot therein that is recessed relative to a primary surface of said electrically conductive flange;

an electrically conductive substrate mounted within the slot;

a dielectric layer on said electrically conductive substrate;

a gate electrode strip line that is patterned on said dielectric layer and extends opposite the electrically conductive substrate, said gate electrode strip line having an upper surface that is coplanar with the primary surface of said electrically conductive flange; and

a vertical power MOSFET having a semiconductor region therein, a source electrode that extends adjacent a first surface of the semiconductor region and is electrically coupled and mounted to a first portion of the primary surface of said flange located outside the slot, a gate electrode that is electrically coupled and mounted to the upper surface at a first end of said gate electrode strip line and a drain electrode that extends adjacent a second surface of the semiconductor region, which is opposite the first surface.

2. The device of claim 1, further comprising:

a drain terminal mounted to said flange and electrically coupled to the drain electrode of said vertical power device; and

a gate terminal mounted to said flange and electrically coupled to said gate electrode strip line.

3. The device of claim 2, further comprising a gate metal strap that electrically connects said gate terminal to a second end of said gate electrode strip line.

4. The device of claim 1, wherein the source electrode of said vertical power MOSFET is electrically connected to the first portion of the flange by a first solder bond;

and wherein the gate electrode is electrically connected to the first end of said gate electrode strip line by a second solder bond.

5. The device of claim 1, wherein said electrically conductive substrate comprises a semiconductor substrate that is electrically connected to said flange.

6. The device of claim 5, further comprising a polysilicon capacitor electrode that is disposed within the slot and is electrically connected to said gate electrode strip line.

7. The device of claim 6, wherein said polysilicon capacitor electrode, said dielectric layer and said semiconductor substrate collectively form a MOS capacitor.

9. The device of claim 1, wherein said gate electrode strip line comprises first and second strip line segments that are joined together by a capacitor electrode;

and wherein the capacitor electrode and said electrically conductive substrate collectively form opposing electrodes of a capacitor.

8. A packaged power transistor, comprising:

an electrically conductive flange having a slot therein that is recessed relative to a primary surface of said electrically conductive flange;

a ceramic substrate mounted within the slot;

a gate electrode strip line that is patterned on said ceramic substrate and extends opposite a bottom of the slot, said gate electrode strip line having an upper surface that is coplanar with the primary surface of said electrically conductive flange; and

a vertical power MOSFET having a semiconductor region therein, a source electrode that extends adjacent a first surface of the semiconductor region and is electrically coupled and mounted to a first portion of said flange located outside the slot, a gate electrode that is electrically coupled and mounted to a first end of said gate electrode strip line and a drain electrode that extends adjacent a second surface of the semiconductor region, which is opposite the first surface.

10. A packaged power transistor device, comprising:

an electrically conductive flange having a slot therein that is recessed relative to a primary surface of said electrically conductive flange;

an integrated circuit substrate mounted to a bottom of the slot, said integrated circuit substrate comprising a semiconductor layer that is electrically coupled to said flange, a dielectric layer on the semiconductor layer and a gate interconnect on the dielectric layer, said gate interconnect comprising a gate electrode strip line having an upper surface that is coplanar with the primary surface of said electrically conductive flange; and

a vertical power MOSFET having a semiconductor region therein, a source electrode that extends adjacent a first surface of the semiconductor region and is electrically coupled and mounted to a first portion of said flange located outside the slot, a gate electrode that is electrically coupled and mounted to the gate interconnect and a drain electrode that extends adjacent a second surface of the semiconductor region, which is opposite the first surface.

11. A packaged power transistor device, comprising:

an electrically conductive flange having a slot therein that is recessed relative to a primary surface of said electrically conductive flange;

an integrated circuit substrate mounted to a bottom of the slot, said integrated circuit substrate comprising a semiconductor layer that is electrically coupled to said flange, a dielectric layer on the semiconductor layer and a gate interconnect on the dielectric layer, said gate interconnect comprising a gate electrode strip line or a gate metal strap; and

a vertical power MOSFET having a semiconductor region therein, a source electrode that extends adjacent a first surface of the semiconductor region and is electrically coupled and mounted to a first portion of said flange located outside the slot, a gate electrode that is electrically coupled and mounted to the gate interconnect and a drain electrode that extends adjacent a second surface of the semiconductor region, which is opposite the first surface;

wherein said gate interconnect comprises a gate electrode strip line;

wherein said gate electrode strip line comprises first and second strip line segments that are joined together by a capacitor electrode;

wherein the capacitor electrode and the semiconductor layer collectively form opposing electrodes of a capacitor; and

wherein an upper surface of said gate electrode strip line is coplanar with the primary surface of said electrically conductive flange.