Method and circuit for testing DC parameters of circuit input and output nodes

• US 6,586,921 B1
• Filed: 05/12/2000
• Issued: 07/01/2003
• Est. Priority Date: 05/12/2000
• Status: Active Grant

• Current Assignee: Mentor Graphics Corporation (Siemens AG)
• Original Assignee: Logicvision, Inc. (Siemens AG)
• Inventors: Sunter, Stephen Kenneth
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): HOLLINGTON, JERMELE M
• Application Number:
  US09/570,412
• Time in Patent Office: 1,145 Days
• Field of Search: 324/76.11, 324/754, 324/763, 324/158.1, 714/726, 714/729, 714/727, 714/724, 371/22.1, 371/21.1, 371/22.5, 371/22.3
• US Class Current: 324/76.11
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/318577 AC testing, e.g. current testing, burn-in
• CPC Class Codes: G01R 31/31858 Delay testing

Abstract

A method and built-in circuit are described for testing direct current (DC) parameters of the input and output pins of a circuit by testing the transition time interval for rising and falling voltage transitions. When the voltage transition is for an integrated circuit (IC) pin having a known capacitance, which can include off-chip capacitance, the magnitude and direction of current at the pin can be determined. The method enables testing an IC via a test access port (TAP) comprising a subset of the pins of the IC, for example in conformance with the IEEE 1149.1 boundary scan test standard. For sufficiently small current magnitudes, such as leakage current (IIL and IIH), the technique can use only on-chip circuitry to sample a pin voltage at time intervals after an output transition is generated at the pin, the time intervals pre-determined to be less than the transition time interval. For larger current magnitudes, such as IOL and IOH, an off-chip capacitance of known value is connected to the pin to decrease the rate of transition. For greater accuracy, an off-chip resistor of known value is connected to the pin, and the transition time interval due to the driver is compared to the transition time interval due to the resistor.

Claims

1. A method for testing current flowing through a circuit node of a circuit under test, the circuit under test including drive circuitry that drives the circuit node to a maximum and to a minimum voltage during testing, and including a logic circuit that samples the logic level of the circuit node synchronously to a clock signal, the circuit node having a capacitance, and the logic circuit having an input switching point voltage, the method comprising the steps of:

(a) driving the circuit node to a known voltage, via the drive circuitry that drives the circuit node;

(b) causing a signal transition at the circuit node via the drive circuitry;

(c) sampling a logic value of a voltage of the circuit node, via the logic circuit, at a predetermined time interval after the beginning of the signal transition, the time interval being less than an expected signal transition time and being proportional to values of the capacitance of the circuit node, the input switching point voltage of the logic circuit, and the current flowing through the circuit node; and

(d) passing or failing the test, based on the logic value sampled by the logic circuit during the signal transition.

2. The method of claim 1, wherein the predetermined time interval having a duration so that, when the current flowing through the capacitance of the circuit node is less than a minimum specified value, the logic circuit generates a failing response in step (d).

3. The method of claim 1 further comprising:

(e) repeating steps (a) to (d) with different predetermined intervals to obtain cumulative test results; and

(f) based on the cumulative test results, deducing a value of a current flowing through the capacitance of the circuit node.

4. The method of claim 1, wherein

step (b) uses a first edge of the test clock to generate the signal transition on the circuit node via the drive circuitry;

step (c) uses a second edge of opposite polarity of the test clock to sample the voltage of the circuit node; and

step (c) uses an interval between the first and second edges as the predetermined interval.

5. The method of claim 1, wherein the circuit under test is compliant with the requirements of the IEEE 1149.1 boundary scan standard, and has a test access port (TAP) controller and a clock controlling the TAP controller.

6. The method and circuit of claim 5, wherein step (c) controls the predetermined time interval by adjusting the frequency of the clock controlling the TAP controller.

7. The method of claim 1, wherein the predetermined time interval having a duration so that, when the current flowing through the capacitance of the circuit node exceeds a maximum specified value, the logic circuit generates a failing response in step (d).

8. The method of claim 7, wherein

step (a) uses as the drive circuitry a 3-state driver having a data input and enable input;

step (b) generates the signal transition by disabling the 3-state driver via the enable input, and then changing the logic value of the data input; and

step (d) provides a failing response indicating that the disabling action did not take effect.

9. The method of claim 1, wherein step (a) drives two circuit nodes using the drive circuitry which is a differential driver that drives both nodes, each circuit node having the logic circuit which is a differential comparator that samples the difference between the voltage at one circuit node and the voltage at the other circuit node.

10. The method of claim 9, wherein

step (a) provides a known capacitance between the two circuit nodes;

and

step (c) uses the value of the known capacitance to determine the predetermined time interval.

11. The method of claim 1, wherein the method and the circuit under test are compliant with the requirements of the IEEE 1149.1 boundary scan standard.

12. The method of claim 11, wherein step (c) controls the predetermined time interval by adjusting the number of clock cycles occurring between an Update-DR state and a Capture-DR state.

13. The method of claim 11, wherein step (c) controls the predetermined time interval by adjusting the frequency of the clock controlling the TAP controller.

14. The method of claim 1, wherein the circuit under test has a known resistance connected between the circuit node and a constant voltage, and step (c) comprises:

(i) deducing a transition time when the known resistance is driving the capacitance, the transition time becoming a reference transition time;

(ii) obtaining a ratio between the known resistance and an output impedance of the drive circuitry; and

(iii) determining the predetermined time interval for passing or failing the drive circuitry based on the reference transition time and the ratio between the known resistance and the output impedance of the drive circuitry.

15. The method of claim 14, wherein step (iii) determines the predetermined time interval so that, when the current conveyed through the circuit node exceeds a maximum specified value, the output of the logic circuit generates a failing response in step (d).

16. The method of claim 14, wherein step (iii) determines the predetermined time interval so that, when the current conveyed through the circuit node is less than a minimum specified value, the output of the logic circuit generates a failing response in step (d).

17. The method of claim 14 further comprising:

(e) repeating steps(a) to (d) with different predetermined intervals to obtain cumulative test results; and

(f) based on the cumulative test results, deducing the value of a current conveyed through the circuit node.

18. The method of claim 1, wherein

the circuit under test has a known resistance connected between the circuit node and a known voltage, the value of the capacitance of the circuit node is known;

step (a) drives the circuit node to the minimum or maximum voltage; and

step (b) disables the drive circuitry to a high impedance state to cause the signal transition to be proportional to the known resistance and the capacitance.

19. The method of claim 18, wherein step (c) determines the predetermined time interval so that, when the switching point voltage of the logic circuit exceeds a maximum specified value, the output of the logic circuit generates a failing response in step (d).

20. The method of claim 19, wherein the input switching point voltage is tested for both rising and falling signal transitions.

21. The method of claim 18, wherein step (c) determines the predetermined time interval so that, when the switching point voltage of the logic circuit is less than a minimum specified value, the output of the logic circuit generates a failing response in step (d).

22. The method of claim 21, wherein the input switching point voltage is tested for both rising and falling signal transitions.

23. The method of claim 18 further comprising:

(e) repeating steps(a) to (d) with different predetermined intervals to obtain cumulative test results; and

(f) based on the cumulative test results, deducing the value of the switching point voltage of the logic circuit.

24. The method of claim 23, wherein the value of the input switching point voltage is deduced for both rising and falling signal transitions.

44. A method as defined in claim 1, said drive circuitry being a 3-state driver having a data input, an enable input, and an output, said circuit having an IEEE 1149.1 compliant test access port (TAP) and a TAP controller, said method testing said enable input of said driver and further comprises:

step (b) includes disabling said driver during an Update-IR state of said TAP controller and changing the logic value of said data input after said driver is disabled and before step (c) is performed;

step (c) comprises capturing the output logic value of said driver during a Capture-DR state of said TAP controller and said time interval being less than the time for a maximum acceptable leakage current to discharge the voltage of said circuit node sufficiently to change the logic value of said circuit node; and

step (d) comprises comparing the sampled output logic value with an expected logic value of a properly functioning driver.

45. A method as defined in claim 44, wherein step (a) comprises driving said circuit node to a maximum voltage;

and after completing step (d), repeating steps (a) to step (d) but with step (a) driving said circuit node to a minimum voltage..

25. A method for testing drive current flowing through a circuit node of a circuit under test, the circuit under test including drive circuitry for driving the circuit node to a maximum and to a minimum voltage during testing, and a logic circuit for sampling the logic level of the circuit node, the circuit node having a capacitance, and the logic circuit having an input switching point voltage, the method comprising the steps of:

determining a time interval for a signal transition on said circuit node that is less than an expected transition time of said signal transition and proportional to values of the capacitance of said circuit node, the input switching point voltage for said circuit node, and the current flowing through said circuit node;

generating a signal transition on the circuit node via the drive circuitry in response to a first edge of a first clock which immediately follows an edge of a test clock used to generate test control signals, said first clock having a significantly higher frequency than said test clock;

sampling a logic value of a voltage of the circuit node via the logic circuit in response to a subsequent edge of said first clock spaced from said first edge by said time interval; and

passing or failing the test based on the sampled logic value of the voltage of the circuit node.

26. The method of claim 25, wherein said determining a time interval including selecting a frequency of said first test clock to provide the determined time interval between said first and subsequent edges of said first test clock.

27. The method of claim 25, wherein the circuit under test is compliant with the requirements of the IEEE 1149.1 boundary scan standard.

28. The method of claim 27, wherein said determining a time interval including selecting a frequency of said first test clock to provide the determined time interval between said first and subsequent edges of said first test clock.

29. A control signal modifying circuit for modifying a test control signal generated by a test controller for controlling drive circuitry that drives a circuit node of a circuit under test and logic circuitry that samples the voltage of the circuit node, the test controller having a test clock for generating the test control signal and transitions between states for the test controller, the control signal modifying circuit comprising:

receiving means for receiving the test control signal generated by the test controller;

modifying means for modifying the test control signal to provide a predetermined time interval which is less than an expected signal transition time and proportional to values of the capacitance of the circuit node, the input switching point voltage of the logic circuit, and the current flowing through the circuit node; and

outputting means for outputting the modified test control signal to the drive circuitry and logic circuitry.

30. The control signal modifying circuit of claim 29, wherein the modifying means includes:

means for detecting a first edge of the test clock which generates the signal transition on the circuit node via the drive circuitry; and

means for detecting a second edge of opposite polarity of the test clock to sample the voltage of the circuit node.

31. The control signal modifying circuit of claim 29, wherein the circuit under test and the test controller are compliant with the requirements of the IEEE 1149.1 boundary scan standard.

32. A control signal modifying circuit for modifying a test control signal generated by a test controller for controlling drive circuitry that drives a circuit node of a circuit under test and logic circuitry that samples the voltage of the circuit node, the test controller having a first test clock for generating the test control signal and transitions between states for the test controller, the control signal modifying circuit comprising:

first receiving means for receiving the first test clock;

second receiving means for receiving a second clock with a significantly higher frequency than the first test clock;

detecting means for detecting an edge of the second test clock, which immediately follows an edge of the first test clock, and generates a signal transition on the circuit node via the drive circuitry;

controlling means for controlling a subsequent edge of the second test clock to sample the voltage of the circuit node, such that a time interval between the edges of the second test clock is less than an expected transition time of the signal transition and proportional to values of the capacitance of the circuit node, the input switching point voltage for the circuit node, and the current flowing through the circuit node.

33. The control signal modifying circuit of claim 32, wherein the controlling means has a frequency adjuster for adjusting the frequency of the second test clock to control the time interval between the edges of the second test clock.

34. The control signal modifying circuit of claim 32, wherein the circuit under test and the test controller are compliant with the requirements of the IEEE 1149.1 boundary scan standard.

35. The control signal modifying circuit of claim 34, wherein the controlling means has a frequency adjuster for adjusting the frequency of the second test clock to control the time interval between the edges of the second test clock.

36. Testing circuitry for testing current flowing through a circuit node of a circuit under test, the circuit node having a capacitance, the testing circuitry comprising:

drive circuitry that drives the circuit node to a maximum and to a minimum voltage during testing;

a logic circuit that samples the logic level of the circuit node synchronously to a clock signal, the logic circuit having an input switching point voltage;

a test controller for controlling the drive circuitry and the logic circuitry, the test controller having a test clock for generating the test control signal and transitions between states for the test controller; and

a control signal modifying circuit for modifying the test control signal to provide a predetermined time interval which is less than an expected signal transition time and proportional to values of the capacitance of the circuit node, the input switching point voltage of the logic circuit, and the current flowing through the circuit node.

37. The testing circuitry of claim 36, wherein the control signal modifying circuit includes:

means for detecting a first edge of the test clock which generates the signal transition on the circuit node via the drive circuitry; and

means for detecting a second edge of opposite polarity of the test clock to sample the voltage of the circuit node.

38. The testing circuitry of claim 36, wherein

the circuit under test and the testing circuitry are compliant with the requirements of the IEEE 1149.1 boundary scan standard.

39. Testing circuitry for testing current flowing through a circuit node of a circuit under test, then circuit node having a capacitance, the testing circuitry comprising:

drive circuitry that drives the circuit node to a maximum and to a minimum voltage during testing;

a logic circuit that samples the logic level of the circuit node synchronously to a clock signal, the logic circuit having an input switching point voltage;

a test controller for controlling the drive circuitry and the logic circuitry, the test controller having a first test clock for generating the test control signal and transitions between states for the test controller;

a control signal modifying circuit having;

first receiving means for receiving the first test clock;

second receiving means for receiving a second clock with a significantly higher frequency than the first test clock;

detecting means for detecting an edge of the second test clock, which immediately follows an edge of the first test clock, and generates a signal transition on the circuit node via the drive circuitry;

controlling means for controlling a subsequent edge of the second test clock to sample the voltage of the circuit node, such that a time interval between the edges of the second test clock is less than an expected transition time of the signal transition and proportional to values of the capacitance of the circuit node, the input switching point voltage for the circuit node, and the current flowing through the circuit node.

40. The testing circuitry of claim 39, wherein the controlling means has a frequency adjuster for adjusting the frequency of the second test clock to control the time interval between the edges of the second test clock.

41. The testing circuitry of claim 39, wherein the circuit under test and the testing circuitry are compliant with the requirements of the IEEE 1149.1 boundary scan standard.

42. The testing circuitry of claim 41, wherein the controlling means has a frequency adjuster for adjusting the frequency of the second test clock to control the time interval between the edges of the second test clock.

43. A circuit for use in testing drive current flowing through a circuit node of a circuit under test, the circuit under test having drive circuitry for driving the circuit node to a maximum and to a minimum voltage during testing, and a logic circuit for sampling the logic level of the circuit node, the circuit node having a capacitance, and the logic circuit having an input switching point voltage, the circuit comprising:

a first circuit for generating a signal transition on the circuit node via said drive circuitry in response to an edge of a first clock which immediately follows an edge of a test clock, said first clock having a higher frequency than said test clock; and

a second circuit for generating a sampling signal for sampling a logic value of the voltage of said circuit node via said logic circuit in response to a subsequent edge of said test clock, said second circuit providing a time interval between said edges of said first clock which is less than an expected transition time of said signal transition and proportional to values of the capacitance of said circuit node, an input switching point voltage for said circuit node, and current flowing through said circuit node.

46. A circuit for use in testing an enable input of a 3-state driver which drives a circuit node of an integrated circuit to a maximum and to a minimum voltage during testing, the driver having a data input, an enable input, and an output, said integrated circuit having an IEEE 1149.1 compliant test access port (TAP) and a TAP controller, and a logic circuit for sampling the logic level of the circuit node, the circuit node having a capacitance, and the logic circuit having an input switching point voltage, the circuit comprising:

means for causing a signal transition at the circuit node via the drive circuitry and for disabling said driver during an Update-IR state of said TAP controller and for changing the logic value of said data input after said driver has been disabled and before sampling the logic value of said circuit node; and

means for sampling a logic value of a voltage of the circuit node via the logic circuit under control of said clock signal at a predetermined time interval after the beginning of said signal transition, said time interval being less than the time for a maximum acceptable leakage current to discharge the voltage of said circuit node sufficiently to change the logic value of said circuit node, and the current flowing through the circuit node, said sampling means capturing the output logic value of said driver during a Capture-DR state of said TAP controller.

47. A method for testing leakage current flowing through a circuit node of a circuit under test, the circuit under test including drive circuitry that drives the circuit node to a maximum and to a minimum voltage during testing, and including a logic circuit that samples the logic level of the circuit node synchronously to a clock signal, the circuit node having a capacitance, and the logic circuit having an input switching point voltage, the method comprising the steps of:

(a) determining a time interval for a signal transition on said circuit node that is less than an expected transition time of said signal transition and proportional to values of the capacitance of said circuit node, the input switching point voltage for said circuit node, and leakage current flowing through said circuit node;

(b) driving the circuit node to a known voltage via the drive circuitry that drives the circuit node;

(c) causing a signal transition at the circuit node via the drive circuitry;

(d) sampling a logic value of a voltage of the circuit node via the logic circuit at a said time interval after the beginning of the signal transition; and

(e) passing or failing the test based on the logic value sampled by the logic circuit during the signal transition.