Differential termination with calibration for differential signaling

• US 6,586,964 B1
• Filed: 12/10/2001
• Issued: 07/01/2003
• Est. Priority Date: 12/10/2001
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Kent, Michael, Nix, Michael A.
• Primary Examiner(s): TAN, VIBOL
• Application Number:
  US10/013,438
• Time in Patent Office: 568 Days
• Field of Search: 326/30, 326/83, 326/86, 326/90, 327/108, 327/362, 333/17.3, 710/100, 710/126
• US Class Current: 326/30
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines

Abstract

A system for calibrating an adjustable termination resistor for a low voltage differential signaling (LVDS) system is provided. The system includes an adjustable termination resistor located on a chip and a reference termination resistor located off the chip. A bias circuit coupled to the adjustable termination resistor and the reference termination resistor causes the same current to flow through the adjustable termination resistor and the reference termination resistor. A comparator is configured to compare a first voltage drop across the adjustable termination resistor and a second voltage drop across the reference termination resistor. A control circuit is coupled to receive an output signal from the comparator. If the output signal indicates that the adjustable termination resistor has a desirable value with respect to the reference termination resistor, then the control circuit stops the calibration operation. Otherwise, the control circuit modifies the adjustable termination resistor and repeats the calibration cycle.

Claims

1. A method of calibrating an adjustable termination resistor for a low voltage differential signaling (LVDS) system, the method comprising:

comparing the resistance of the adjustable termination resistor against the resistance of an external reference resistor; and

adjusting the resistance of the adjustable termination resistor in response to the resistance of the external resistor.

2. The method of claim 1, wherein the step of comparing comprises:

biasing the external reference resistor and the adjustable termination resistor in the same manner;

comparing a voltage drop across the external reference resistor and a voltage drop across the adjustable termination resistor; and

adjusting the resistance of the adjustable termination resistor in response to the step of comparing.

3. The method of claim 2, wherein the biasing step comprises:

routing a first current through the external reference resistor; and

routing a second current through the adjustable termination resistor, wherein the first current is equal to the second current.

4. The method of claim 2, wherein the comparing step comprises:

providing a first voltage representative of the voltage drop across the adjustable termination resistor to a first input terminal of a comparator; and

providing a second voltage representative of the voltage drop across the external reference resistor to a second input terminal of the comparator; and

generating an output signal with the comparator that indicates whether the first voltage is greater than the second voltage.

5. The method of claim 1, wherein the adjustable termination resistor is adjusted by selectively enabling and disabling transistors within the adjustable termination resistor.

6. The method of claim 1, further comprising biasing a mid-point of the adjustable termination at a predetermined voltage level.

7. The method of claim 1, wherein the steps of comparing and adjusting are performed during a first half of a duty cycle, and a second half of the duty cycle is idle.

8. The method of claim 1, wherein the step of adjusting the resistance comprises enabling and disabling transistors having binary-weighted resistances.

9. The method of claim 1, wherein the step of adjusting the resistance comprises enabling and disabling transistors having linearly-weighted resistances.

10. The method of claim 1, further comprising:

generating a control signal representative of the adjusted resistance of the adjustable termination resistor; and

transmitting the control signal to adjust the resistance of other adjustable termination resistors.

11. A system for calibrating an adjustable termination resistor for a low voltage differential signaling (LVDS) system, the system comprising:

an adjustable LVDS termination resistor located on a chip;

a reference termination resistor located off the chip;

a bias circuit coupled to the adjustable termination resistor and the reference termination resistor, wherein the bias circuit causes the same current to flow through the adjustable termination resistor and the reference termination resistor;

a comparator configured to compare a first voltage drop across the adjustable termination resistor and a second voltage drop across the reference termination resistor; and

a control circuit coupled to receive an output signal from the comparator, and in response, provide an adjustment control signal to adjust the resistance of the adjustable termination resistor.

12. The system of claim 11, further comprising:

a first pair of pads on the chip, wherein the adjustable termination resistor is coupled between the first pair of pads; and

a second pair of pads on the chip, wherein the reference termination resistor is coupled between the second pair of pads.

13. The system of claim 11, wherein the adjustable termination resistor comprises:

a first resistor having a first terminal coupled to a first pad;

a second resistor having a first terminal coupled to a second pad; and

a plurality of transistors connected in parallel between a second terminal of the first resistor and a second terminal of the second resistor.

14. The system of claim 13, wherein the first resistor and the second resistor together exhibit a resistance more than half of the resistance of the reference termination resistor.

15. The system of claim 13, wherein the control circuit controls which transistors in the plurality of transistors are turned on.

16. The system of claim 13, wherein the control circuit is coupled to provide the adjustment control signal to adjust the resistances of a plurality of adjustable termination resistors.

17. The system of claim 13, wherein the adjustable termination resistor has a resistance that is adjustable between 90 and 120 Ohms.

18. The system of claim 13, wherein the plurality of transistors are configured to form a plurality of transfer gates, each of the transfer gates comprising a p-channel transistor and an n-channel transistor coupled in parallel.

19. The system of claim 11, wherein the adjustable termination resistor comprises:

a first resistor, a second resistor, a third resistor and a fourth resistor connected in series, wherein the first resistor and the fourth resistor are located at the ends of the series connection;

a set of p-channel transistors connected in parallel with the second and third resistors; and

a set of n-channel transistors connected in parallel with the second and third resistors.

20. The system of claim 19, wherein the first, second, third and fourth resistors comprise n-type polycrystalline silicon.

21. The system of claim 19, wherein the set of p-channel transistors exhibit binary weighted resistances when turned on.

22. The system of claim 19, wherein the set of n-channel transistors exhibit binary weighted resistances when turned on.

23. The system of claim 19, further comprising a bias circuit coupled to a node between the second and third resistors, the bias circuit maintaining the node at a predetermined voltage.

24. The system of claim 23, wherein the bias circuit is further coupled a bulk region of the set of p-channel transistors, wherein the bias circuit maintains the bulk region of the p-channel transistors at the predetermined voltage.

25. The system of claim 23, wherein the predetermined voltage is less than a V_DD supply voltage.

26. The system of claim 23, wherein the control circuit is configured to control the p-channel transistors and the n-channel transistors that are turned on.

27. The system of claim 23, further comprising:

a first pad, wherein the first resistor and the reference termination resistor are coupled to the first pad;

a second pad, wherein the reference termination resistor is coupled to the second pad;

a first current source coupled to the fourth resistor; and

a second current source, identical to the first current source, coupled to the second pad.

28. The system of claim 27, wherein the comparator is coupled to the second pad and the fourth resistor.

29. The system of claim 19, wherein the resistance of the first and fourth resistors is less than the resistance of the second and third resistors.

30. The system of claim 29, wherein the resistance of the first and fourth resistors is about half the resistance of the second and third resistors.